Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits
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1 Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits Tae-Hyoung Kim, Randy Persaud and Chris H. Kim Department of Electrical and Computer Engineering University of Minnesota, Minneapolis
2 Outline NBTI Overview Previous NBTI Measurement Method Proposed Silicon Odometer Circuit Beat Frequency Detection Scheme Test Chip Measurement Results Voltage and Temperature Dependency DC and AC Conclusions 2
3 Negative Bias Temperature Instability SiH + h + Si + + H One of the most critical reliability issues today Holes in inversion layer interact with Si-H bonds at interface when device is under stress (V gs = -V dd ), leave interface traps NBTI manifests itself as an increase in V tp 3
4 and Recovery When a stressed PMOS is turned off Si-H bond breaking stops H diffused back to Si/SiO 2 interface and anneals broken bonds AC stress increases lifetime projection Increasing field and temperature, reduced gate overdrive reintroduce NBTI concerns in the late 90s 4
5 NBTI Signal Probability Dependence SP= SP=0.5 SP=0.25 V tp (mv) SP=.0 SP=0.75 SP=0.5 SP= Time (s) Device is stressed when input signal is low Signal Probability (SP): Probability that the input signal is low NBTI effect is SP dependent 5
6 NBTI Impact on Digital Circuits WL i 6 3 o BLB BL i o 2 V L V R i Logic circuits F MAX degrades Leakage power reduces Memory circuits Read margin worsens Write stability improves Read delay remains the same NBTI affects critical circuit parameters Need to design circuits with NBTI-induced shifts comprehended 6
7 Circuit Techniques to Mitigate the Impact of NBTI Degradation Product margin-testing, guard-banding Size up devices Negates benefits of scaling, increases power Toggle circuit nodes Less degradation under AC stress Lower temperature Difficult task now dense/fast designs are hot Progressive V tp and V dd tuning We can slowly increase V dd or forward body bias PMOS as performance degrades with aging (Intel, ISSCC07) Bottom line: Need to accurately measure the NBTI effect and develop compact models 7
8 Previous NBTI Measurement Technique V cc_ring Ring Osc./ Critical Path Replica Counter F = F rosc /N F = F rosc Before After V. Reddy et al., IRPS, 2002 Measure ring oscillator frequency shift Main limitations Low sensing resolution (few % frequency change) Sensitive to environmental variation during measurement Invasive, not suitable for run-time monitoring 8
9 Proposed Silicon Odometer Circuit V DD_STR V DD_NOM 0V Measurement period ed ROSC (freq=f stress ) A B Reference ROSC Phase Comp. C PC_OUT (freq=f ref -f stress ) (freq=f ref ) Two free running ROSCs for beat frequency detection Sample stressed ROSC output using reference ROSC output Count PC_OUT to determine frequency degradation Insensitive to environmental variation 9
10 Principle of Silicon Odometer Circuit A B C ed ROSC Reference ROSC N. f ref (freq=f stress ) (freq=f ref ) PC_OUT (freq=f ref -f stress ) -Before stress N. = (N ). f ref f stress -After stress N. = (N ). f - % frequency degradation f stress - fstress N - N = f N ( N-) Operation example % delay difference before stress N = 00 2% delay difference after stress N = 50 N changes by 50 for % change in delay sub-ps resolution degradation measurements stress ref f stress 0
11 Sensing Resolution Comparison Counter output (N) Proposed Conventional % % Frequency degradation (%) 33 High delay sensing resolution For N=00 and T=4ns, maximum sensing resolution is 0.4ps (0.0%)
12 Test Chip Architecture Control signals (Meas_stress, Toggle, OSC_en) Ring oscillator (reference) ROSC_ REF B 8-bit counter Reset N Register Reset Scan out DETECT Control signals (Meas_stress, AC_stress, AC_CLK, Recv_stress ) Ring oscillator (stressed) ROSC frequency trimming ROSC_ STRESS A Phase compar - ator C bit majority voting ckt. Bubble rejection DETECT D Beat freq. detector 0000 N. f ref Frequency trimming capacitors set the initial frequency difference between the stressed and reference ROSC 5 bit majority voting circuit for bubble rejection 2
13 Ring Oscillator Circuit Design ROSC Frequency Trimming V DD Control S0 S S2 S3 S4 Meas_ AC_ Recv_ V 2 0 DD_STRESS V DD_NOM C Virtual V DD 2 C. 2 2 C 2 3 C 2 4 C Measurement mode Meas_ AC_ AC_CLK Toggle Mode Control # mode Mode Control #2 4ns ROSC period, frequency trimming capacitors mode and measurement mode Meas_ triggers the measurement 3
14 Various /Recovery Modes V DD Control Meas _ AC_ Recv _ V DD_STRESS V DD_NOM Virtual V DD. Measurement mode Meas _ AC_ AC_CLK Toggle Mode Control # mode Mode Control #2 <µs Meas_ Meas. Meas. Meas. Mode Meas_ AC_ Toggle DC_ w/ toggle 0 DC_ w/o toggle 0 0 AC_ X Measurement 0 0 X 4
15 Phase Comparator Circuit Design CLK CLK: Delayed RSOC_REF ROSC_REF ROSC_STRESS B A A CLK CLK PC_OUT CLK CLK CLK CLK B A PC_OUT Beat frequency Delayed ROSC_REF used as reference clock Dynamic circuit implementation PC_OUT contains the beat frequency 5
16 Simulated Waveforms DETECT Beat frequency Latency VOTE _OUT (D in Fig. 4) PC_OUT (C in Fig. 4) ROSC _REF (B in Fig. 4) ROSC_STRESS (A in Fig. 4) 3 ROSC cycles of measurement latency Static signal from 5b majority voting circuit DETECT signal gives beat frequency 6
17 Test Chip Implementation Measurement work bench Labview GUI 0.3µm MM/RF CMOS, 265 x 32 µm 2 layout area ed and reference ROSCs have identical layout Chips were not recycled since once stressed, they will not fully recover 7
18 Odometer Measurement Results and recovery behavior Temperature dependency Frequency degradation 0.30% 0.25% 0.20% 0.5% 0.0% 0.05%.2V, 30 C Frequency degradation 0.35% 0.30% 0.25% 0.20% 0.5% 0.0% 0.05% 30 C,.2V DC stress 30 C,.2V DC stress 0.00% 0.00% Time (sec) Time (sec) Resolution high enough (<0.02% or <0.8ps) for nonaccelerated stress measurements 80% recovery rate due to relatively thick T ox Worse degradation at higher temperature 8
19 Voltage Dependency.00%.2V DC stress, 30C.8V DC stress, 30C 0.67% Frequency degradation y = x 0.58 y = x % 0.0% Time (sec) Degradation exponentially dependent on the electric field Delay degradation has same power-law dependency as ΔV tp 9
20 DC versus AC 0.80%.8V, 30 C Frequency degradation 0.70% 0.60% 0.50% 0.40% 0.30% 0.20% 0.0% AC stress (20MHz) AC stress (GHz) DC stress 0.67% 0.38% 0.33% 0.00% Time (sec) AC stress results in 43-50% less frequency degradation Weak frequency dependency Many baby steps takes you same distance as a few giant steps This behavior also confirmed by recursive RD models 20
21 Conclusions NBTI is a growing threat to circuit reliability On-chip NBTI monitor circuits are needed to understand aging impact on circuits Silicon odometer circuit demonstrated Fully digital, minimal calibration Sub-picosecond sensing resolution Sub-microsecond measurement time for minimal annealing Differential measurement eliminates common-mode environmental variation impact Acknowledgements: IBM for financial support and UMC for chip fabrication 2
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