RTN Induced Frequency Shift Measurements Using a Ring Oscillator Based Circuit

Size: px
Start display at page:

Download "RTN Induced Frequency Shift Measurements Using a Ring Oscillator Based Circuit"

Transcription

1 RTN Induced Frequency Shift Measurements Using a Ring Oscillator Based Circuit Qianying Tang 1, Xiaofei Wang 1, John Keane 2, and Chris H. Kim 1 1 University of Minnesota, Minneapolis, MN 2 Intel Corporation, Hillsboro, OR Symposia on VLSI Technology and Circuits

2 Background Outline Proposed ROSC Based RTN Characterization Circuit 65nm Test Chip RTN Data Transistor V t Shift Estimation Summary Slide 1

3 Random Telegraph Noise (RTN) Basics Random trapping and de-trapping of carriers from channel Manifests as a fluctuation in V t resembling a random telegraph signal Slide 2

4 RTN Characterization Techniques Probing Individual transistor SRAM VDD Circuit based methods Logic circuit or ring oscillator Schematic WL WL D Q BL BLB Parameter of interest DC current SRAM V min Frequency shift Pros 1. Simple 2. High resolution 1. Realistic RTN impact on SRAM V min 2. Short test time 3. Small test area 1. Realistic RTN impact on circuit frequency 2. Short test time 3. Small test area Cons 1. Long test time 2. Large test area 3. Limited insight on circuit level 1. Limited resolution 2. Rare occurrences 3. Averaging effect 1. Limited resolution 2. Long meas. time 3. Averaging effect Slide 3

5 Simple ROSC Based Meas. Circuit Measure the divided ROSC frequency using offchip instrument A simple & popular structure for characterizing process variation and reliability issues No reported RTN data using this technique Single ended sensing, common mode noise, long measurement time poor resolution Slide 4

6 Beat Frequency Detection Scheme C A B T. Kim, et al., JSSC, 2008 D flip-flop captures the beat frequency of two free running ROSCs Benefits of beat frequency detection scheme Achieves <0.01% frequency measurement resolution at sub-microsecond sampling times Insensitive to common mode noise such as V, T drifts Fully-digital scan-based interface Slide 5

7 RTN Measurements Using BFD Scheme RTN Slide 6

8 RTN Measurements Using BFD Scheme RTN Slide 7

9 RTN Measurements Using BFD Scheme RTN Slide 8

10 RTN Measurements Using BFD Scheme RTN Small frequency shifts induced by RTN amplified Sub-ps resolution + sub-µs measurement time Slide 9

11 Comparison with Prior Art Counter Counter Counter [2] K. Ito, et al., IRPS, 2011 Slide 10

12 ROSC Based Test Chip Diagram Row Select DUT ROSC DUT ROSC DUT ROSC Column Select DUT ROSC DUT ROSC DUT ROSC row<n> col<m> DUT ROSC DUT ROSC DUT ROSC N:1 Mux Ref. ROSC A B A B 8bit Counter DFF D Beat Frequency Detection Unit Q C Reset Edge Detector Parallel/serial shift register Scan out An 8 10 DUT ROSC array, a shared reference ROSC and a beat frequency detection block Measure beat frequency between DUT ROSC and shared reference ROSC Slide 11

13 65nm Test Chip Die Photo Slide 12

14 ROSC Frequency Shift Measurements Single trap induced ROSC frequency shift is roughly 0.4% at 0.8V Capture/emission time constants range from 1 ms to 100 s of milliseconds Slide 13

15 Single and Multi Trap RTN Time Lag Plot (TLP) used to identify the number of RTN traps [3] [3] T. Nagumo, et al., IEDM, 2009 Slide 14

16 Frequency Shift versus Voltage f/f (%) Peak-to-peak f/f (%) Frequency shift due to RTN trap decreases at higher voltages Frequency shift sensitivity decreases Fermi level shifts with supply voltage Slide 15

17 Time Constant Distribution τ c =3.68 ms τ e =14.0 ms τ c =24.9 ms τ e =8.12 ms τ c =26.7 ms τ e =8.70 ms Capture and emission time fit exponential distribution under AC condition Pr = A exp(-t/τ) Slide 16

18 Time Constant versus Voltage τ c and τ e show opposite dependences τ c has negative dependence on voltage for NMOS and positive dependence for PMOS [3] [3] T. Nagumo, et al., IEDM, 2009 Slide 17

19 Power Spectral Density of RTN PSD of RTN induced frequency shift suggests a Lorentzian spectrum Slide 18

20 Number of Traps Distribution Most ROSCs do not show any RTN behavior No more than two RTN inducing traps observed Slide 19

21 Frequency to V t Mapping Frequency shift is proportional to V t shift V t shift due to single RTN trap is 1.9% for NMOS and 1.6% for PMOS Slide 20

22 V t Shift versus Supply Voltage Freq. shift reduces at higher supply voltages However, trap induced V t shift has a weak dependency on supply voltage Slide 21

23 Summary Beat frequency detection system utilized for high precision RTN measurement with short measurement time ROSC frequency shift due to RTN measured for the first time from a 65nm test chip Single trap RTN causes 0.4% frequency shift at 0.8V Wide range of time constants measured Frequency shift and time constant measured at different supply voltages Measured ROSC frequency data can be readily mapped to transistor V t shift Slide 22

Duty-Cycle Shift under Asymmetric BTI Aging: A Simple Characterization Method and its Application to SRAM Timing

Duty-Cycle Shift under Asymmetric BTI Aging: A Simple Characterization Method and its Application to SRAM Timing Duty-Cycle Shift under Asymmetric BTI Aging: A Simple Characterization Method and its Application to SRAM Timing 1 Xiaofei Wang, 2 John Keane, 2 Pulkit Jain, 3 Vijay Reddy and 1 Chris H. Kim 1 University

More information

Fast Characterization of PBTI and NBTI Induced Frequency Shifts under a Realistic Recovery Bias Using a Ring Oscillator Based Circuit

Fast Characterization of PBTI and NBTI Induced Frequency Shifts under a Realistic Recovery Bias Using a Ring Oscillator Based Circuit Fast Characterization of PBTI and NBTI Induced Frequency Shifts under a Realistic Recovery Bias Using a Ring Oscillator Based Circuit 1,2 Xiaofei Wang, 1 Seung-hwan Song, 1 Ayan Paul and 1 Chris H. Kim

More information

Impact of Interconnect Length on. Degradation

Impact of Interconnect Length on. Degradation Impact of Interconnect Length on BTI and HCI Induced Frequency Degradation Xiaofei Wang, Pulkit Jain, Dong Jiao and Chris H. Kim University of Minnesota, Minneapolis, MN xfwang@umn.edu www.umn.edu/~chriskim/

More information

SRAM Read Performance Degradation under Asymmetric NBTI and PBTI Stress: Characterization Vehicle and Statistical Aging

SRAM Read Performance Degradation under Asymmetric NBTI and PBTI Stress: Characterization Vehicle and Statistical Aging SRAM Read Performance Degradation under Asymmetric NBTI and PBTI Stress: Characterization Vehicle and Statistical Aging Xiaofei Wang,2 Weichao Xu 2 and Chris H. Kim 2 Intel Corporation, Hillsboro 2 University

More information

RANDOM telegraph noise (RTN) has become an increasing

RANDOM telegraph noise (RTN) has become an increasing IEEE JOURNAL OF SOLID-STATE CIRCUITS 1 Characterizing the Impact of RTN on Logic and SRAM Operation Using a Dual Ring Oscillator Array Circuit Qianying Tang, Student Member, IEEE, andchrish.kim,senior

More information

Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits

Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits Tae-Hyoung Kim, Randy Persaud and Chris H. Kim Department of Electrical and Computer Engineering

More information

True Random Number Generator Circuits Based on Single- and Multi- Phase Beat Frequency Detection

True Random Number Generator Circuits Based on Single- and Multi- Phase Beat Frequency Detection True Random Number Generator Circuits Based on Single- and Multi- Phase Beat Frequency Detection Qianying Tang, Bongjin Kim, Yingjie Lao, Keshab K. Parhi, and Chris H. Kim University of Minnesota, Minneapolis,

More information

Duty-Cycle Shift under Asymmetric BTI Aging: A Simple Characterization Method and its Application to SRAM Timing 1 Xiaofei Wang

Duty-Cycle Shift under Asymmetric BTI Aging: A Simple Characterization Method and its Application to SRAM Timing 1 Xiaofei Wang Duty-Cycle Shift under Asymmetric BTI Aging: A Simple Characterization Method and its Application to SRAM Timing 1 Xiaofei Wang Abstract the effect of DC BTI stress on the clock signal's dutycycle has

More information

University of Minnesota, Minneapolis, MN 2. Intel Corporation, Hillsboro, OR 3. Los Alamos National Laboratory, Los Alamos, NM

University of Minnesota, Minneapolis, MN 2. Intel Corporation, Hillsboro, OR 3. Los Alamos National Laboratory, Los Alamos, NM Statistical Characterization of Radiation- Induced Pulse Waveforms and Flip-Flop Soft Errors in 14nm Tri-Gate CMOS Using a Back- Sampling Chain (BSC) Technique Saurabh Kumar 1, M. Cho 2, L. Everson 1,

More information

SILICON ODOMETERS:COMPACT IN SITU AGING SENSORS FOR ROBUST SYSTEM DESIGN

SILICON ODOMETERS:COMPACT IN SITU AGING SENSORS FOR ROBUST SYSTEM DESIGN ... SILICON ODOMETERS:COMPACT IN SITU AGING SENSORS FOR ROBUST SYSTEM DESIGN... THIS ARTICLE REVIEWS SEVERAL TEST-CHIP DESIGNS THAT DEMONSTRATE THE BENEFITS Xiaofei Wang University of Minnesota John Keane

More information

Impact of Interconnect Length on BTI and HCI Induced Frequency Degradation

Impact of Interconnect Length on BTI and HCI Induced Frequency Degradation Impact of Interconnect Length on BTI and HCI Induced Frequency Degradation Xiaofei Wang Pulkit Jain Dong Jiao Chris H. Kim Department of Electrical & Computer Engineering University of Minnesota 200 Union

More information

An Array-Based Circuit for Characterizing Latent Plasma-Induced Damage

An Array-Based Circuit for Characterizing Latent Plasma-Induced Damage An Array-Based Circuit for Characterizing Latent Plasma-Induced Damage Won Ho Choi, Pulkit Jain and Chris H. Kim University of Minnesota, Minneapolis, MN choi0444@umn.edu www.umn.edu/~chriskim/ Purpose

More information

A 10Gb/s 10mm On-Chip Serial Link in 65nm CMOS Featuring a Half-Rate Time-Based Decision Feedback Equalizer

A 10Gb/s 10mm On-Chip Serial Link in 65nm CMOS Featuring a Half-Rate Time-Based Decision Feedback Equalizer A 10Gb/s 10mm On-Chip Serial Link in 65nm CMOS Featuring a Half-Rate Time-Based Decision Feedback Equalizer Po-Wei Chiu, Somnath Kundu, Qianying Tang, and Chris H. Kim University of Minnesota, Minneapolis,

More information

A Data Remanence based Approach to Generate 100% Stable Keys from an SRAM Physical Unclonable Function

A Data Remanence based Approach to Generate 100% Stable Keys from an SRAM Physical Unclonable Function A Data Remanence based Approach to Generate 100% Stable Keys from an SRAM Physical Unclonable Function Muqing Liu, Chen Zhou, Qianying Tang, Keshab K. Parhi and Chris H. Kim University of Minnesota, Twin

More information

All-Digital PLL Frequency and Phase Noise Degradation Measurements Using Simple On-Chip Monitoring Circuits

All-Digital PLL Frequency and Phase Noise Degradation Measurements Using Simple On-Chip Monitoring Circuits All-Digital PLL Frequency and Noise Degradation Measurements Using Simple On-Chip Monitoring Circuits Gyusung Park, Minsu Kim and Chris H. Kim Department of Electrical and Computer Engineering University

More information

Electronic Circuits EE359A

Electronic Circuits EE359A Electronic Circuits EE359A Bruce McNair B206 bmcnair@stevens.edu 201-216-5549 1 Memory and Advanced Digital Circuits - 2 Chapter 11 2 Figure 11.1 (a) Basic latch. (b) The latch with the feedback loop opened.

More information

Analysis of Low Power-High Speed Sense Amplifier in Submicron Technology

Analysis of Low Power-High Speed Sense Amplifier in Submicron Technology Voltage IJSRD - International Journal for Scientific Research & Development Vol. 2, Issue 02, 2014 ISSN (online): 2321-0613 Analysis of Low Power-High Speed Sense Amplifier in Submicron Technology Sunil

More information

A mm 2 /Channel Time-Based Beat Frequency ADC in 65nm CMOS for Intra-Electrode Neural Recording

A mm 2 /Channel Time-Based Beat Frequency ADC in 65nm CMOS for Intra-Electrode Neural Recording A 0.0094mm 2 /Channel Time-Based Beat Frequency ADC in 65nm CMOS for Intra-Electrode Neural Recording Luke Everson 1, Somnath Kundu 1, Gang Chen 2, Zhi Yang 3, Timothy J. Ebner 2, and Chris H. Kim 1 1

More information

Method for Qcrit Measurement in Bulk CMOS Using a Switched Capacitor Circuit

Method for Qcrit Measurement in Bulk CMOS Using a Switched Capacitor Circuit Method for Qcrit Measurement in Bulk CMOS Using a Switched Capacitor Circuit John Keane Alan Drake AJ KleinOsowski Ethan H. Cannon * Fadi Gebara Chris Kim jkeane@ece.umn.edu adrake@us.ibm.com ajko@us.ibm.com

More information

UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency

UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency UMAINE ECE Morse Code ROM and Transmitter at ISM Band Frequency Jamie E. Reinhold December 15, 2011 Abstract The design, simulation and layout of a UMAINE ECE Morse code Read Only Memory and transmitter

More information

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010 817 An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB John Keane, Student Member, IEEE, Xiaofei Wang, Student

More information

Lecture 7: Components of Phase Locked Loop (PLL)

Lecture 7: Components of Phase Locked Loop (PLL) Lecture 7: Components of Phase Locked Loop (PLL) CSCE 6933/5933 Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors pages,

More information

A 0.2-to-1.45GHz Subsampling Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection

A 0.2-to-1.45GHz Subsampling Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection A 0.2-to-1.45GHz Subsampling Fractional-N All-Digital MDLL with Zero-Offset Aperture PD-Based Spur Cancellation and In-Situ Timing Mismatch Detection Somnath Kundu 1, Bongjin Kim 1,2, Chris H. Kim 1 1

More information

ECEN 720 High-Speed Links Circuits and Systems

ECEN 720 High-Speed Links Circuits and Systems 1 ECEN 720 High-Speed Links Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by transmitters.

More information

Defect-Oriented Degradations in Recent VLSIs: Random Telegraph Noise, Bias Temperature Instability and Total Ionizing Dose

Defect-Oriented Degradations in Recent VLSIs: Random Telegraph Noise, Bias Temperature Instability and Total Ionizing Dose Defect-Oriented Degradations in Recent VLSIs: Random Telegraph Noise, Bias Temperature Instability and Total Ionizing Dose Kazutoshi Kobayashi Kyoto Institute of Technology Kyoto, Japan kazutoshi.kobayashi@kit.ac.jp

More information

CHAPTER 7 A BICS DESIGN TO DETECT SOFT ERROR IN CMOS SRAM

CHAPTER 7 A BICS DESIGN TO DETECT SOFT ERROR IN CMOS SRAM 131 CHAPTER 7 A BICS DESIGN TO DETECT SOFT ERROR IN CMOS SRAM 7.1 INTRODUCTION Semiconductor memories are moving towards higher levels of integration. This increase in integration is achieved through reduction

More information

Fully Parallel 6T-2MTJ Nonvolatile TCAM with Single-Transistor-Based Self Match-Line Discharge Control

Fully Parallel 6T-2MTJ Nonvolatile TCAM with Single-Transistor-Based Self Match-Line Discharge Control Fully Parallel 6T-2MTJ Nonvolatile TCAM with Single-Transistor-Based Self Match-Line Discharge Control Shoun Matsunaga 1,2, Akira Katsumata 2, Masanori Natsui 1,2, Shunsuke Fukami 1,3, Tetsuo Endoh 1,2,4,

More information

NXP. P5CC052 Secure Contact PKI Smart Card Controller. Analog Circuit Analysis

NXP. P5CC052 Secure Contact PKI Smart Card Controller. Analog Circuit Analysis NXP P5CC052 Secure Contact PKI Smart Card Controller Analog Circuit Analysis 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com Some of the information

More information

On-Chip Silicon Odometers and their Potential Use in Medical Electronics

On-Chip Silicon Odometers and their Potential Use in Medical Electronics On-Chip Silicon Odometers and their Potential Use in Medical Electronics John Keane 1 and Chris H. Kim 1. Intel Corporation, Technology and Manufacturing Group, Hillsboro, OR, USA. University of Minnesota,

More information

A VCO-Based ADC Employing a Multi- Phase Noise-Shaping Beat Frequency Quantizer for Direct Sampling of Sub-1mV Input Signals

A VCO-Based ADC Employing a Multi- Phase Noise-Shaping Beat Frequency Quantizer for Direct Sampling of Sub-1mV Input Signals A VCO-Based ADC Employing a Multi- Phase Noise-Shaping Beat Frequency Quantizer for Direct Sampling of Sub-1mV Input Signals Bongjin Kim, Somnath Kundu, Seokkyun Ko and Chris H. Kim University of Minnesota,

More information

Design For Test Technique for Leakage Power Reduction in Nanoscale Static Random Access Memory

Design For Test Technique for Leakage Power Reduction in Nanoscale Static Random Access Memory Journal of Computer Science 7 (8): 1252-1260, 2011 ISSN 1549-3636 2011 Science Publications Design For Test Technique for Leakage Power Reduction in Nanoscale Static Random Access Memory N.M. Sivamangai

More information

A CMOS Image Sensor with Ultra Wide Dynamic Range Floating-Point Pixel-Level ADC

A CMOS Image Sensor with Ultra Wide Dynamic Range Floating-Point Pixel-Level ADC A 640 512 CMOS Image Sensor with Ultra Wide Dynamic Range Floating-Point Pixel-Level ADC David X.D. Yang, Abbas El Gamal, Boyd Fowler, and Hui Tian Information Systems Laboratory Electrical Engineering

More information

電子電路. Memory and Advanced Digital Circuits

電子電路. Memory and Advanced Digital Circuits 電子電路 Memory and Advanced Digital Circuits Hsun-Hsiang Chen ( 陳勛祥 ) Department of Electronic Engineering National Changhua University of Education Email: chenhh@cc.ncue.edu.tw Spring 2010 2 Reference Microelectronic

More information

ECEN 720 High-Speed Links: Circuits and Systems

ECEN 720 High-Speed Links: Circuits and Systems 1 ECEN 720 High-Speed Links: Circuits and Systems Lab4 Receiver Circuits Objective To learn fundamentals of receiver circuits. Introduction Receivers are used to recover the data stream transmitted by

More information

Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies

Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies Low-Power and Process Variation Tolerant Memories in sub-9nm Technologies Saibal Mukhopadhyay, Swaroop Ghosh, Keejong Kim, and Kaushik Roy Dept. of ECE, Purdue University, West Lafayette, IN, @ecn.purdue.edu

More information

ECEN 720 High-Speed Links: Circuits and Systems. Lab3 Transmitter Circuits. Objective. Introduction. Transmitter Automatic Termination Adjustment

ECEN 720 High-Speed Links: Circuits and Systems. Lab3 Transmitter Circuits. Objective. Introduction. Transmitter Automatic Termination Adjustment 1 ECEN 720 High-Speed Links: Circuits and Systems Lab3 Transmitter Circuits Objective To learn fundamentals of transmitter and receiver circuits. Introduction Transmitters are used to pass data stream

More information

! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements

! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute.  From state elements ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential

More information

CMOS Analog VLSI Design Prof. A N Chandorkar Department of Electrical Engineering Indian Institute of Technology, Bombay. Lecture - 24 Noise

CMOS Analog VLSI Design Prof. A N Chandorkar Department of Electrical Engineering Indian Institute of Technology, Bombay. Lecture - 24 Noise CMOS Analog VLSI Design Prof. A N Chandorkar Department of Electrical Engineering Indian Institute of Technology, Bombay Lecture - 24 Noise Various kinds of noise and is this morning and we discussed that

More information

An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization

An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization 2374 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 10, OCTOBER 2011 An Array-Based Odometer System for Statistically Significant Circuit Aging Characterization John Keane, Member, IEEE, Wei Zhang,

More information

/$ IEEE

/$ IEEE IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 53, NO. 11, NOVEMBER 2006 1205 A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for

More information

EE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector

EE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector EE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector Group Members Uttam Kumar Boda Rajesh Tenukuntla Mohammad M Iftakhar Srikanth Yanamanagandla 1 Table

More information

Available online at ScienceDirect. International Conference On DESIGN AND MANUFACTURING, IConDM 2013

Available online at  ScienceDirect. International Conference On DESIGN AND MANUFACTURING, IConDM 2013 Available online at www.sciencedirect.com ScienceDirect Procedia Engineering 64 ( 2013 ) 377 384 International Conference On DESIGN AND MANUFACTURING, IConDM 2013 A Novel Phase Frequency Detector for a

More information

Memory Basics. historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities

Memory Basics. historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities Memory Basics RAM: Random Access Memory historically defined as memory array with individual bit access refers to memory with both Read and Write capabilities ROM: Read Only Memory no capabilities for

More information

D f ref. Low V dd (~ 1.8V) f in = D f ref

D f ref. Low V dd (~ 1.8V) f in = D f ref A 5.3 GHz Programmable Divider for HiPerLAN in 0.25µm CMOS N. Krishnapura 1 & P. Kinget 2 Lucent Technologies, Bell Laboratories, USA. 1 Currently at Columbia University, New York, NY, 10027, USA. 2 Currently

More information

CMOS 65nm Process Monitor

CMOS 65nm Process Monitor CMOS 65nm Process Monitor Final Report Fall Semester 2008 Prepared to partially fulfill the requirements for ECE401 Department of Electrical and Computer Engineering Colorado State University Fort Collins,

More information

Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018

Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018 Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018 ECE 658 Sp 2018 Semiconductor Materials and Device Characterizations OUTLINE Background FinFET Future Roadmap Keeping up w/ Moore s Law

More information

Variation Aware Performance Analysis of Gain Cell Embedded DRAMs

Variation Aware Performance Analysis of Gain Cell Embedded DRAMs Variation Aware Performance Analysis of Gain Cell Embedded DRAMs Wei Zhang Department of ECE University of Minnesota Minneapolis, MN zhang78@umn.edu Ki Chul Chun Department of ECE University of Minnesota

More information

Random telegraph signal noise simulation of decanano MOSFETs subject to atomic scale structure variation

Random telegraph signal noise simulation of decanano MOSFETs subject to atomic scale structure variation Superlattices and Microstructures 34 (2003) 293 300 www.elsevier.com/locate/superlattices Random telegraph signal noise simulation of decanano MOSFETs subject to atomic scale structure variation Angelica

More information

Receiver Design for Passive Millimeter Wave (PMMW) Imaging

Receiver Design for Passive Millimeter Wave (PMMW) Imaging Introduction Receiver Design for Passive Millimeter Wave (PMMW) Imaging Millimeter Wave Systems, LLC Passive Millimeter Wave (PMMW) sensors are used for remote sensing and security applications. They rely

More information

SUBTHRESHOLD logic circuits are becoming increasingly

SUBTHRESHOLD logic circuits are becoming increasingly 518 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 2, FEBRUARY 2008 A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing Tae-Hyoung Kim, Student Member, IEEE,

More information

SIMMAT A Metastability Analysis Tool

SIMMAT A Metastability Analysis Tool SIMMAT A Metastability Analysis Tool Simulation waveforms voltage d q Ian W. Jones and Suwen Yang, Oracle Labs, Mark Greenstreet, University of British Columbia clk time (ns) 1 November 2012 1 Outline

More information

Self-Calibration Technique for Reduction of Hold Failures in Low-Power Nano-scaled SRAM

Self-Calibration Technique for Reduction of Hold Failures in Low-Power Nano-scaled SRAM Self-Calibration Technique for Reduction of Hold Failures in Low-Power Nano-scaled SRAM Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, and, Kaushik Roy School of Electrical and Computer Engineering,

More information

DESIGN & IMPLEMENTATION OF SELF TIME DUMMY REPLICA TECHNIQUE IN 128X128 LOW VOLTAGE SRAM

DESIGN & IMPLEMENTATION OF SELF TIME DUMMY REPLICA TECHNIQUE IN 128X128 LOW VOLTAGE SRAM DESIGN & IMPLEMENTATION OF SELF TIME DUMMY REPLICA TECHNIQUE IN 128X128 LOW VOLTAGE SRAM 1 Mitali Agarwal, 2 Taru Tevatia 1 Research Scholar, 2 Associate Professor 1 Department of Electronics & Communication

More information

Contributions on the automatic tuning of LC networks using on-chip circuits. Paulo Márcio Moreira e Silva Radiofrequency Laboratory

Contributions on the automatic tuning of LC networks using on-chip circuits. Paulo Márcio Moreira e Silva Radiofrequency Laboratory Contributions on the automatic tuning of LC networks using on-chip circuits Paulo Márcio Moreira e Silva Radiofrequency Introduction 1 Motivation: Real world problem. Ceitec s ID earring used by the cattle.

More information

Design and analysis of 6T SRAM cell using FINFET at Nanometer Regime Monali S. Mhaske 1, Prof. S. A. Shaikh 2

Design and analysis of 6T SRAM cell using FINFET at Nanometer Regime Monali S. Mhaske 1, Prof. S. A. Shaikh 2 Design and analysis of 6T SRAM cell using FINFET at Nanometer Regime Monali S. Mhaske 1, Prof. S. A. Shaikh 2 1 ME, Dept. Of Electronics And Telecommunication,PREC, Maharashtra, India 2 Associate Professor,

More information

Static Random Access Memory - SRAM Dr. Lynn Fuller Webpage:

Static Random Access Memory - SRAM Dr. Lynn Fuller Webpage: ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Static Random Access Memory - SRAM Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Email:

More information

Design and Implement of Low Power Consumption SRAM Based on Single Port Sense Amplifier in 65 nm

Design and Implement of Low Power Consumption SRAM Based on Single Port Sense Amplifier in 65 nm Journal of Computer and Communications, 2015, 3, 164-168 Published Online November 2015 in SciRes. http://www.scirp.org/journal/jcc http://dx.doi.org/10.4236/jcc.2015.311026 Design and Implement of Low

More information

Intellect Amplifier, Current Clasped and Filled Current Approach Sense Amplifiers Techniques Based Low Power SRAM

Intellect Amplifier, Current Clasped and Filled Current Approach Sense Amplifiers Techniques Based Low Power SRAM Intellect Amplifier, Current Clasped and Filled Current Approach Sense Amplifiers Techniques Based Low Power SRAM V. Karthikeyan 1 1 Department of ECE, SVSCE, Coimbatore, Tamilnadu, India, Karthick77keyan@gmail.com

More information

Low Power Design of Schmitt Trigger Based SRAM Cell Using NBTI Technique

Low Power Design of Schmitt Trigger Based SRAM Cell Using NBTI Technique Low Power Design of Schmitt Trigger Based SRAM Cell Using NBTI Technique M.Padmaja 1, N.V.Maheswara Rao 2 Post Graduate Scholar, Gayatri Vidya Parishad College of Engineering for Women, Affiliated to JNTU,

More information

Team VeryLargeScaleEngineers Robert Costanzo Michael Recachinas Hector Soto. High Speed 64kb SRAM. ECE 4332 Fall 2013

Team VeryLargeScaleEngineers Robert Costanzo Michael Recachinas Hector Soto. High Speed 64kb SRAM. ECE 4332 Fall 2013 Team VeryLargeScaleEngineers Robert Costanzo Michael Recachinas Hector Soto High Speed 64kb SRAM ECE 4332 Fall 2013 Outline Problem Design Approach & Choices Circuit Block Architecture Novelties Layout

More information

Current Mode Interconnect

Current Mode Interconnect Department Of Electrical Engineering Indian Institute Of Technology, Bombay March 21, 2009 Inductive peaking: Concept Inductive Peaking for Bandwith Enhancement On-chip interconnects can be modeled as

More information

MTJ based Random Number Generation and Analog-to-Digital Conversion Chris H. Kim University of Minnesota

MTJ based Random Number Generation and Analog-to-Digital Conversion Chris H. Kim University of Minnesota MTJ based Random Number Generation and Analog-to-Digital Conversion Chris H. Kim University of Minnesota Workshop on the Future of Spintronics, June 5, 216 1 Switching Probability of an MTJ Parallel: Low

More information

A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting

A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting Jonggab Kil Intel Corporation 1900 Prairie City Road Folsom, CA 95630 +1-916-356-9968 jonggab.kil@intel.com

More information

Semiconductor Memory: DRAM and SRAM. Department of Electrical and Computer Engineering, National University of Singapore

Semiconductor Memory: DRAM and SRAM. Department of Electrical and Computer Engineering, National University of Singapore Semiconductor Memory: DRAM and SRAM Outline Introduction Random Access Memory (RAM) DRAM SRAM Non-volatile memory UV EPROM EEPROM Flash memory SONOS memory QD memory Introduction Slow memories Magnetic

More information

arxiv: v1 [cond-mat.other] 4 Apr 2017

arxiv: v1 [cond-mat.other] 4 Apr 2017 Analysis and validation of low-frequency noise reduction in MOSFET circuits using variable duty cycle switched biasing Kapil Jainwal, Mukul Sarkar, and Kushal Shah Department of Electrical Engineering,

More information

REDUCING power consumption and enhancing energy

REDUCING power consumption and enhancing energy 548 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 63, NO. 6, JUNE 2016 A Low-Voltage PLL With a Supply-Noise Compensated Feedforward Ring VCO Sung-Geun Kim, Jinsoo Rhim, Student Member,

More information

Design and Implementation of High Speed Sense Amplifier for Sram

Design and Implementation of High Speed Sense Amplifier for Sram American-Eurasian Journal of Scientific Research 12 (6): 320-326, 2017 ISSN 1818-6785 IDOSI Publications, 2017 DOI: 10.5829/idosi.aejsr.2017.320.326 Design and Implementation of High Speed Sense Amplifier

More information

Lecture 6: Electronics Beyond the Logic Switches Xufeng Kou School of Information Science and Technology ShanghaiTech University

Lecture 6: Electronics Beyond the Logic Switches Xufeng Kou School of Information Science and Technology ShanghaiTech University Lecture 6: Electronics Beyond the Logic Switches Xufeng Kou School of Information Science and Technology ShanghaiTech University EE 224 Solid State Electronics II Lecture 3: Lattice and symmetry 1 Outline

More information

PROGRAMMABLE ASIC INTERCONNECT

PROGRAMMABLE ASIC INTERCONNECT ASICs...THE COURSE (1 WEEK) PROGRAMMABLE ASIC INTERCONNECT 7 Key concepts: programmable interconnect raw materials: aluminum-based metallization and a line capacitance of 0.2pFcm 1 7.1 Actel ACT Actel

More information

EVALUATION OF RADIATION HARDNESS DESIGN TECHNIQUES TO IMPROVE RADIATION TOLERANCE FOR CMOS IMAGE SENSORS DEDICATED TO SPACE APPLICATIONS

EVALUATION OF RADIATION HARDNESS DESIGN TECHNIQUES TO IMPROVE RADIATION TOLERANCE FOR CMOS IMAGE SENSORS DEDICATED TO SPACE APPLICATIONS EVALUATION OF RADIATION HARDNESS DESIGN TECHNIQUES TO IMPROVE RADIATION TOLERANCE FOR CMOS IMAGE SENSORS DEDICATED TO SPACE APPLICATIONS P. MARTIN-GONTHIER, F. CORBIERE, N. HUGER, M. ESTRIBEAU, C. ENGEL,

More information

Analysis and Simulation of a Low-Leakage 6T FinFET SRAM Cell Using MTCMOS Technique at 45 nm Technology

Analysis and Simulation of a Low-Leakage 6T FinFET SRAM Cell Using MTCMOS Technique at 45 nm Technology Analysis and Simulation of a Low-Leakage 6T FinFET SRAM Cell Using MTCMOS Technique at 45 nm Technology Shyam Sundar Sharma 1, Ravi Shrivastava 2, Nikhil Saxenna 3 1Research Scholar Dept. of ECE, ITM,

More information

Low Power Design of Successive Approximation Registers

Low Power Design of Successive Approximation Registers Low Power Design of Successive Approximation Registers Rabeeh Majidi ECE Department, Worcester Polytechnic Institute, Worcester MA USA rabeehm@ece.wpi.edu Abstract: This paper presents low power design

More information

A New Capacitive Sensing Circuit using Modified Charge Transfer Scheme

A New Capacitive Sensing Circuit using Modified Charge Transfer Scheme 78 Hyeopgoo eo : A NEW CAPACITIVE CIRCUIT USING MODIFIED CHARGE TRANSFER SCHEME A New Capacitive Sensing Circuit using Modified Charge Transfer Scheme Hyeopgoo eo, Member, KIMICS Abstract This paper proposes

More information

DOUBLE DATA RATE (DDR) technology is one solution

DOUBLE DATA RATE (DDR) technology is one solution 54 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 2, NO. 6, JUNE 203 All-Digital Fast-Locking Pulsewidth-Control Circuit With Programmable Duty Cycle Jun-Ren Su, Te-Wen Liao, Student

More information

Read/Write Stability Improvement of 8T Sram Cell Using Schmitt Trigger

Read/Write Stability Improvement of 8T Sram Cell Using Schmitt Trigger International Journal of Scientific and Research Publications, Volume 5, Issue 2, February 2015 1 Read/Write Stability Improvement of 8T Sram Cell Using Schmitt Trigger Dr. A. Senthil Kumar *,I.Manju **,

More information

A Novel Multiplier Design using Adaptive Hold Logic to Mitigate BTI Effect

A Novel Multiplier Design using Adaptive Hold Logic to Mitigate BTI Effect GRD Journals Global Research and Development Journal for Engineering International Conference on Innovations in Engineering and Technology (ICIET) - 2016 July 2016 e-issn: 2455-5703 A Novel Multiplier

More information

Microelectronics Reliability

Microelectronics Reliability Microelectronics Reliability 50 (2010) 1039 1053 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel Introductory Invited Paper On-chip

More information

Design and Implementation of Digital CMOS VLSI Circuits Using Dual Sub-Threshold Supply Voltages

Design and Implementation of Digital CMOS VLSI Circuits Using Dual Sub-Threshold Supply Voltages RESEARCH ARTICLE OPEN ACCESS Design and Implementation of Digital CMOS VLSI Circuits Using Dual Sub-Threshold Supply Voltages A. Suvir Vikram *, Mrs. K. Srilakshmi ** And Mrs. Y. Syamala *** * M.Tech,

More information

DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT

DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT DESIGN AND VERIFICATION OF ANALOG PHASE LOCKED LOOP CIRCUIT PRADEEP G CHAGASHETTI Mr. H.V. RAVISH ARADHYA Department of E&C Department of E&C R.V.COLLEGE of ENGINEERING R.V.COLLEGE of ENGINEERING Bangalore

More information

SiNANO-NEREID Workshop:

SiNANO-NEREID Workshop: SiNANO-NEREID Workshop: Towards a new NanoElectronics Roadmap for Europe Leuven, September 11 th, 2017 WP3/Task 3.2 Connectivity RF and mmw Design Outline Connectivity, what connectivity? High data rates

More information

(12) Patent Application Publication (10) Pub. No.: US 2011/ A1

(12) Patent Application Publication (10) Pub. No.: US 2011/ A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2011/0188326 A1 Lee et al. US 2011 0188326A1 (43) Pub. Date: Aug. 4, 2011 (54) DUAL RAIL STATIC RANDOMACCESS MEMORY (75) Inventors:

More information

Southern Methodist University Dallas, TX, Southern Methodist University Dallas, TX, 75275

Southern Methodist University Dallas, TX, Southern Methodist University Dallas, TX, 75275 Single Event Effects in a 0.25 µm Silicon-On-Sapphire CMOS Technology Wickham Chen 1, Tiankuan Liu 2, Ping Gui 1, Annie C. Xiang 2, Cheng-AnYang 2, Junheng Zhang 1, Peiqing Zhu 1, Jingbo Ye 2, and Ryszard

More information

A Fast Locking Digital Phase-Locked Loop using Frequency Difference Stage

A Fast Locking Digital Phase-Locked Loop using Frequency Difference Stage International Journal of Engineering & Technology IJET-IJENS Vol:14 No:04 75 A Fast Locking Digital Phase-Locked Loop using Frequency Difference Stage Mohamed A. Ahmed, Heba A. Shawkey, Hamed A. Elsemary,

More information

Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits

Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits Microelectronics Journal 39 (2008) 1714 1727 www.elsevier.com/locate/mejo Temperature-adaptive voltage tuning for enhanced energy efficiency in ultra-low-voltage circuits Ranjith Kumar, Volkan Kursun Department

More information

IC Layout Design of 4-bit Universal Shift Register using Electric VLSI Design System

IC Layout Design of 4-bit Universal Shift Register using Electric VLSI Design System IC Layout Design of 4-bit Universal Shift Register using Electric VLSI Design System 1 Raj Kumar Mistri, 2 Rahul Ranjan, 1,2 Assistant Professor, RTC Institute of Technology, Anandi, Ranchi, Jharkhand,

More information

Introduction to CMOS RF Integrated Circuits Design

Introduction to CMOS RF Integrated Circuits Design VI. Phase-Locked Loops VI-1 Outline Introduction Basic Feedback Loop Theory Circuit Implementation VI-2 What is a PLL? A PLL is a negative feedback system where an oscillatorgenerated signal is phase and

More information

Dr. K.B.Khanchandani Professor, Dept. of E&TC, SSGMCE, Shegaon, India.

Dr. K.B.Khanchandani Professor, Dept. of E&TC, SSGMCE, Shegaon, India. Design and Implementation of High Performance, Low Dead Zone Phase Frequency Detector in CMOS PLL based Frequency Synthesizer for Wireless Applications Priti N. Metange Asst. Prof., Dept. of E&TC, MET

More information

A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and ±35 ps Jitter

A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and ±35 ps Jitter University of Pennsylvania ScholarlyCommons epartmental Papers (ESE) epartment of Electrical & Systems Engineering 7-1-2003 A Fully Integrated CMOS Phase-Locked Loop With 30MHz to 2GHz Locking Range and

More information

Analyzing Combined Impacts of Parameter Variations and BTI in Nano-scale Logical Gates

Analyzing Combined Impacts of Parameter Variations and BTI in Nano-scale Logical Gates Analyzing Combined Impacts of Parameter Variations and BTI in Nano-scale Logical Gates Seyab Khan Said Hamdioui Abstract Bias Temperature Instability (BTI) and parameter variations are threats to reliability

More information

Sleepy Keeper Approach for Power Performance Tuning in VLSI Design

Sleepy Keeper Approach for Power Performance Tuning in VLSI Design International Journal of Electronics and Communication Engineering. ISSN 0974-2166 Volume 6, Number 1 (2013), pp. 17-28 International Research Publication House http://www.irphouse.com Sleepy Keeper Approach

More information

+1 (479)

+1 (479) Introduction to VLSI Design http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable

More information

레이저의주파수안정화방법및그응용 박상언 ( 한국표준과학연구원, 길이시간센터 )

레이저의주파수안정화방법및그응용 박상언 ( 한국표준과학연구원, 길이시간센터 ) 레이저의주파수안정화방법및그응용 박상언 ( 한국표준과학연구원, 길이시간센터 ) Contents Frequency references Frequency locking methods Basic principle of loop filter Example of lock box circuits Quantifying frequency stability Applications

More information

1. Introduction. Volume 6 Issue 6, June Licensed Under Creative Commons Attribution CC BY. Sumit Kumar Srivastava 1, Amit Kumar 2

1. Introduction. Volume 6 Issue 6, June Licensed Under Creative Commons Attribution CC BY. Sumit Kumar Srivastava 1, Amit Kumar 2 Minimization of Leakage Current of 6T SRAM using Optimal Technology Sumit Kumar Srivastava 1, Amit Kumar 2 1 Electronics Engineering Department, Institute of Engineering & Technology, Uttar Pradesh Technical

More information

Effect of W/L Ratio on SRAM Cell SNM for High-Speed Application

Effect of W/L Ratio on SRAM Cell SNM for High-Speed Application Effect of W/L Ratio on SRAM Cell SNM for High-Speed Application Akhilesh Goyal 1, Abhishek Tomar 2, Aman Goyal 3 1PG Scholar, Department Of Electronics and communication, SRCEM Banmore, Gwalior, India

More information

CMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits

CMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits Lec Sequential CMOS Logic Circuits Sequential Logic In Combinational Logic circuit Out Memory Sequential The output is determined by Current inputs Previous inputs Output = f(in, Previous In) The regenerative

More information

[Vivekanand*, 4.(12): December, 2015] ISSN: (I2OR), Publication Impact Factor: 3.785

[Vivekanand*, 4.(12): December, 2015] ISSN: (I2OR), Publication Impact Factor: 3.785 IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY DESIGN AND IMPLEMENTATION OF HIGH RELIABLE 6T SRAM CELL V.Vivekanand*, P.Aditya, P.Pavan Kumar * Electronics and Communication

More information

A Study on the Characteristics of a Temperature Sensor with an Improved Ring Oscillator

A Study on the Characteristics of a Temperature Sensor with an Improved Ring Oscillator Proceedings of the World Congress on Electrical Engineering and Computer Systems and Science (EECSS 2015) Barcelona, Spain July 13-14, 2015 Paper No. 137 A Study on the Characteristics of a Temperature

More information

CMOS technology, which possesses the advantages of low

CMOS technology, which possesses the advantages of low IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 9, SEPTEMBER 2005 2061 Excess Low-Frequency Noise in Ultrathin Oxide n-mosfets Arising From Valence-Band Electron Tunneling Jun-Wei Wu, Student Member,

More information

Forward bias operation of irradiated silicon detectors A.Chilingarov Lancaster University, UK

Forward bias operation of irradiated silicon detectors A.Chilingarov Lancaster University, UK 1 st Workshop on Radiation hard semiconductor devices for very high luminosity colliders, CERN, 28-30 November 2001 Forward bias operation of irradiated silicon detectors A.Chilingarov Lancaster University,

More information

if the conductance is set to zero, the equation can be written as following t 2 (4)

if the conductance is set to zero, the equation can be written as following t 2 (4) 1 ECEN 720 High-Speed Links: Circuits and Systems Lab1 - Transmission Lines Objective To learn about transmission lines and time-domain reflectometer (TDR). Introduction Wires are used to transmit clocks

More information