Fully Parallel 6T-2MTJ Nonvolatile TCAM with Single-Transistor-Based Self Match-Line Discharge Control

Transcription

1 Fully Parallel 6T-2MTJ Nonvolatile TCAM with Single-Transistor-Based Self Match-Line Discharge Control Shoun Matsunaga 1,2, Akira Katsumata 2, Masanori Natsui 1,2, Shunsuke Fukami 1,3, Tetsuo Endoh 1,2,4, Hideo Ohno 1,2, and Takahiro Hanyu 1,2 1 Center for Spintronics Integrated Systems, Tohoku University 2 Research Institute of Electrical Communication, Tohoku University 3 NEC Corporation 4 Center for Interdisciplinary Research, Tohoku University Acknowledgment: This research is supported by the Japan Society for the Promotion of Science (JSPS) through its "Funding Program for World-Leading Innovative R&D on Science and Technology (FIRST Program)." Symposia on VLSI Technology and Circuits June 17, 2011.

2 Outline Background & Purpose 6T-2MTJ-Based NV-TCAM Cell and Test Chip Fabrication Design Example of Low-Power NV-TCAM Using Three-Level Segmented Match-Line Scheme Conclusions Slide 1

3 Background TCAM (Ternary Content-Addressable Memory) Fully Parallel equality-search High-speed pattern matching Applications: Database, virus checker, network router, etc. Demands: Large capacity, Low-power consumption Search word X X X 1 0 X X Parallel Input &Output Hit Hit TCAM cell structure 2-bit volatile storage Comp. Logic Leakage current Problems: Many device counts of TCAM cell Large cell area Increasing leakage current High standby power Purpose : Realize a compact and low-power TCAM Slide 2

4 Merits of MTJ-Based Nonvolatile Logic-in-Memory MTJ device Hardware structure Function MTJ layer CMOS layer Storage Logic Nonvolatile storage Perfectly cut off the power supply. Low standby power 3D-stacking structure Greatly reduce area overhead of storage. Compact CMOS/MTJ-hybrid logic Merge storage and logic functions. More compact Nonvolatile Logic-in-Memory structure is suitable for a compact and low-standby-power TCAM. Slide 3

5 Approaches for a Compact and Low-Power TCAM For Large Capacity (Small Cell Size) Utilize nonvolatile logic-in-memory - 3D-stacking structure - CMOS/MTJ-hybrid logic Compact ( & Nonvolatile) For Low Power (with maintaining search speed) Eliminate wasted cell activation Power OFF at standby state using nonvolatility NV-TCAM cell Low active power Low standby power Match-line (ML) 100% of activity High Power Large capacitive load Small load (Fast) Decreased activity Low Power Disabled (Standby) Medium load (Medium speed) Total load is the same Comparable speed Slide 4

6 Outline Background & Purpose 6T-2MTJ-Based NV-TCAM Cell and Test Chip Fabrication Design Example of Low-Power NV-TCAM Using Three-Level Segmented Match-Line Scheme Conclusions Slide 5

7 Mem. (b 1 ) Cell circuit S Conventional TCAM Cell S Comparison circuit Mem. (b 2 ) ML Match Line GND 2-bit Volatile Mem. (SRAM cells) Large cell size (16Tr. or 12Tr.) High leakage Stored data Input Matched result B (b 1, b 2 ) S ML 0 (0, 1) 1 (1, 0) X Don t care Truth table (0, 0) 0 1 (Hit) 1 0 () 0 0 () 1 1 (Hit) 0 1 (Hit) Masked 1 ML = b 1. S + b 2. S It is desirable to realize a compact and nonvolatile TCAM cell. Slide 6

8 ML VDD BIAS Proposed NV-TCAM Cell 6T-2MTJ NV-TCAM cell WL1 SL(S) ML voltage Keeper (Diode switch) Load SL(S) WL2 I CELL [µa] Measured I-V char. VCELL_H VCELL_L (Hit) () Hit b 1. S + b 2. S b 1 b V CELL-L V CELL (0.35V) V CELL-H BL BL Nonvolatile storage Comparison circuit 20 0 PMOS load VCELL [V] Slide 7

9 Mechanism of ML voltage keeper Minimum voltage detection Match-line (ML) V ML OUT ML voltage keeper Comp. Circuit V CELL Comp. Circuit 1-bit cell If Full-bit Hit V ML : H If V ML : L ML voltage keeper Comp. Circuit V ML is almost the same as minimum voltage of each V CELL. V CELL = V CELL_H (Hit) V CELL_L () Easy to sense Slide 8

10 Self Match-Line Discharge Control in Word Circuit H Full-bit Hit V ML > V CELL_H H H ML is precharged to V DD. ML GND H V ML > V CELL_H H M ML GND V ML = V CELL_H ML GND V ML = V CELL_H M ML GND V ML V DD V CELL_H V CELL_L Slight degradation Hit ML voltage swing Time V ML.. V CELL_L ML GND Slide 9

11 Match-Line Voltage Swing 1-bit miss detection (worst case) Reversed Hit Hit current Hit VCELL-H VCELL-H VCELL-H I Diode Word length Current into a miss cell (exponential scale) Reversed current from hit cells (linear scale) V ML V ML ML voltage keeper (Weak inversion) V CELL-L V CELL-L logarithmic scale V CELL-H VML-L VML-H V ML Sufficient ML voltage swing can be obtained even in longer word circuit. Slide 10

12 Fabricated NV-TCAM Test Chip Column Dec µm 3.36 µm Fabricated TCAM cell 226 µm Row Dec. 2-kb TCAM cell array Sense Amp. Process Cell structure MTJ size 90 nm 1P5M CMOS/MTJ 6T-2MTJ 100 nm x 200 nm Cell size µm µm Array configuration Match delay 32bits x 64words 0.29 ns Supply voltage 1.2 V Slide 11

13 Match-Line Voltage Swings (Simulated and Measured) Match-line voltage swing [V] MRR=400% MRR=250% MRR=172% (Typical) MRR=172% (10% Vth, 10% MRR) MRR=100% Measured V ML : 0.23V@32bits Criterion for sufficient voltage swing Logarithmically degraded Estimated V ML : 0.19V@144bits Easy to detect Word length [bit] Sufficient match-line voltage swing is obtained. Slide 12

14 Chip Measurements RMTJ [kω] R AP R P MRR = x 100 R P = 172% R AP = 3.0 kω R P = 1.1 kω I MTJ [µa] Voltages CLK SL Input key OUT P E P E 1 0 Hit Time P : Precharge E : Evaluate 100ns 1.2V Basic behaviors of the fabricated MTJ device and NV-TCAM have been successfully confirmed. Slide 13

15 Measured Waveforms of Instant-ON/OFF Voltages V DD Power OFF Power OFF Power OFF Power OFF 1.2V Power OFF 1µs CLK SL Input key OUT The same The same 1 output 1 0 output 0 Hit Hit Time Instant ON/OFF of the fabricated chip has been successfully confirmed. Slide 14

16 Outline Background & Purpose 6T-2MTJ-Based NV-TCAM Cell and Test Chip Fabrication Design Example of Low-Power NV-TCAM Using Three-Level Segmented Match-Line Scheme Conclusions Slide 15

17 Approach for Low-Power NV-TCAM Three-Level Segmented Match-Line Scheme 1st segment 2nd segment 3rd segment Hit Disabled Disabled Disabled cell Hit cell If current segment is, then next segment is disabled. Decreased activity rate Low-Power Slide 16

18 Image of Cell Array Activity m-word x n-bit cell array i bits j bits n - i - j bits Hit probability of cell (p): 2/3 (using masked bit) 1/2 (not using masked bit) p i m (1 - p i )m (Active) Hit (Active) Disabled (Inactive) (Active) Hit (Active) Most words are Disabled (Inactive) Enabled (Active) Ultra Low Activity Hit Slide 17

19 Cell Activity Rate Activity rate of cells [%] Minimum activity 1st 3-bit / 2nd 7-bit segmentation % Word length of 1st segment [bit] Word length of 2nd segment [bit] Slide 18

20 Performance Evaluations Array structure 144-bit x 256-word Cell activity [%] 2.8 Search energy [fj/bit/search] 1.04 (Comparable to CMOS-based TCAM within a few fj/bit/search) Standby power [W] Sleep mode Search mode 0 (@Power-OFF) Negligible (@2.8% activity) HSPICE simulation under a 90nm CMOS Low-standby-power nonvolatile TCAM is successfully realized under comparable search energy with CMOS-based one. Slide 19

21 Outline Background & Purpose 6T-2MTJ-Based NV-TCAM Cell and Test Chip Fabrication Design Example of Low-Power NV-TCAM Using Three-Level Segmented Match-Line Scheme Conclusions Slide 20

22 Conclusions We have proposed and demonstrated 6T-2MTJ-based fully-parallel NV-TCAM. Cell Circuit Techniques: - Fewest transistor counts with nonvolatility - Bit-parallel equality-search capability in a long word based on 1-transistor ML voltage keeper array Word Circuit Techniques: - Eliminate wasted cell activation based on three-level segmented match-line scheme Negligible standby power under comparable search energy with CMOS-based TCAM Slide 21