A Study of The Advancement of CMOS ALU & Full Adder Circuit Design For Modern Design

Transcription

1 A Study of The Advancement of & Full Adder Circuit Design F Modern Design Bruce Hardy BR Department of Electrical and Computer Engineering University of Central Flida Orlando, FL

2 Abstract This paper focuses on the design of Full Adder circuits and the improvement of the technology from The is an integral part of modern computing and design innovations today focus mainly on size, speed and power consumption. These will be the main focus of this analysis because of the increased demand f improvement in these metrics. The most interesting designs discovered that improved this field of study were Bridge Style Minity Carrier and Double Gated Polarity Controlled Transists. Keywds, Full Adder, Power Consumption, Delay, Area, logic, bit, I. INTRODUCTION and FPU design are a hot topics in computing because they are at the heart of modern computers. The is responsible f all math functions, ranging from addition to multiplication, logic functions (OR, AND, INV) and comparison commands which can control and monit the computer's vital functions. Calculations of the these numbers are imptant both the computer's functionality and to a user s unique computing needs. This paper will examine 3 imptant metrics to modern design: power consumption, speed, and size because modern design is focused mainly on size and efficiency. An is an Arithmetic Logic Unit which is responsible f a variety of arithmetic and bitwise operations. An FPU is a Floating Point Unit and does the same job as the but with floating point numbers. They are imptant components of the Central Processing Unit CPU, in all computers. An takes in 4 input operands a control signal, A, B, and a Carry In and outputs a single value and a carry out. The input and output operands are tied to the data path between the CPU and the register so that values can be saved and used later in other operations. The is also connected to a control signal that determines what operation is being perfmed and which output the user will see. The data bus width is determined by the device, f example a 64 bit device would have 64 wires in its data path. This is because a wire can only hold one voltage at a time (either 1 0 represented by a set of voltages). The computer's architecture is made such that vital functions are closest to the motherboard to improve not only speed but consume less energy. One such rule of thumb that exists is, ITRS International technology Roadmap f Semiconducts, it is used as a standard f creating semiconduct devices. It determines the basic channel lengths, metal-oxide thickness and other parameters that are imptant to the functionality of semiconduct devices. Execution time is a measure of time used to describe the length of time a program in this case an operation takes to complete. Power dissipation is a term that refers to the power absbed by an element in a circuit, so in the CPU scope it is the power consumed by a component within the computer. Energy Consumption of the process is used as an umbrella term to describe the total power response of a CPU. The subsequent sections of this paper will further detail the advancement of technology. Section II will examine published papers of the subject of full adder designs between the years of 2002 and 2015 and Section III will present data to help visualize the progression of this technology. II. LITERATURE REVIEW From 2002 to 2008 there were many interesting designs researched. The benchmark system that will be used f comparison in this paper was realized using reconfigurable logic in 2002 [5]. The results showed a reduction in delay, area and power metrics compared to previous years examined. The design using only 8 transists absbs 0.5mW of power. The design was made using Multi-Input Floating Gate Mosfet Transists and was comprised of 4 stages, two 2-1 MUXes and a full adder f each. From there a design in 2004 decreased the total delay time 3.2 fold (from ps down to 8100 ps) [6]. This 32-bit decreased its size by 50% and its speed by 70% compared to its rival the NIOS 1.1. In 2005 a full adder using a tree structure architecture was realized using the newer 0.18µm energy efficient technology [4]. This design showed improvement in the output drivability of the circuit. With a 0.8V power supply it used only 0.918µw with 1.4ns of delay. The trend in improvement from 2002 to 2005 in both power and delay can be seen in the graphs presented within the data section below. The final design examined within this time frame was a full adder design using and Magnetic Tunnel Junction technology [7]. Compared to our benchmark 2002 system the total delay improved by fold (from ps to 219 ps). This design had no static power consumption with a dynamic power consumption of 16.3µw which was a 4.3 fold increase compared to standard technology. From massive leaps in most perfmance metrics were realized. A high speed carbon nanotube FET full adder in 2009 [2] clocks a total delay of ps, a 2000 plus fold increase from the benchmark 2002 system. With a 0.9V power supply this design consumed 3.4µw of power. This circuit along with many others after 2002 used the 0.18µm fabrication process. In 2011 a high speed fuller adder was developed using minity function and a bridge style f nano scale purposes [1]. This design had the lowest power consumption of all design examined, 0.294µw, an 11.5 fold increase from The fuller adder design from 2013 [3] using a double gating technique improves in size with a chip area of 2.86 µm 2, a 22 fold improvement when compared to This trend can be seen in the Area graph in the data section below. The digitally controlled double gating technique cuts down on delay time as well, f 8 bit operands 1

3 the total delay was found to be 171 ps. Finally the 2015 All Spin Logic based fuller adder [8] displays the best results f size and delay time. Total delay time was found to be 1.2 ps (a 182 fold increase from 2008) and the size of the chip was decreased to 0.69µm 2 (a 65 fold increase from 2011). The spintronic technology examined in this paper had no power leakage, which is an extradinary accomplishment. Spin device technology is still being researched fully and me designs will come about within the next 4 years that will further improve what our computers can do. III. DATA ANALYSIS This section will display graphs that show the trends in power consumption, area and delay time f full adder designs between 2002 and There is benchmark graphs that use the values from 2002 design as the comparison to switch subsequent year s perfmance is compared. In sht all the graphs show a significant trend of increase despite some outlying data. The reason f outlying data is due to a smaller sample size and the differing in the size (in bits) of the input and output operands of each design presented. Fig. 3. Shows the rate of change in chip area from years The values above are measured in micrometers 2. Fig. 4. Shows comparison of the power consumption benchmark of years after 2002 with the values from The increase is displayed as per fold as it was presented in section II above. Fig. 1. Shows the the rate of change in the power consumption metric from years Values above are measured in microwatts. Fig. 2. Shows the rate of change in the delay time metric from years Values above are measured in Picoseconds. Fig. 5. Shows comparison of the response time benchmark of years after 2002 with the values from 2002.The increase is displayed as per fold as it was presented in section II above. 2

4 IV. CONCLUSION In summation several trends in the design and improvement of full adder circuits from were observed above. The desire f a faster clock rate with increased data and process bus sizes ensures that power consumption, and size will always be among the top sought attributes f the modern computer market. Carbon nanotube FETS and spin device technology are just a few of the brilliant innovations of the last decade. Moe s Law from module 8 can be observed from the presented data. As the size of these micro calculating computers is decreasing exponentially year after year, the number of transists on chip is increasing. The supply voltages are also becoming increasingly small as the devices themselves are shrinking. The design f low voltage is challenging because as the supply voltage is decreased the circuit delays and switching times increase. The Ripple Carry Adder design and tree architecture from module 9 lecture had a common appearance throughout many of the designs examined in this paper. The simultaneous and sequential calculation of variables can save both energy and time. I learned from this study that the best designs are the simplest ones, it s the basics of semiconduct technology that appear most frequently. I noticed that the alteration of variables such gate length, and substrate material are imptant to the design process as they can affect delay and energy consumption. There was no other notable trends observed in the data, this is most likely due to the smaller sample size. As previously stated some fluctuations in the some of the data values was also because of the difference in size (bits) of the input operands of each design examined. The completion of this paper showed me that after taking this class I have a functioning understanding of computer architecture and the computing process that happens within. REFERENCES [1] K. Navi, H. H. Sajedi, R. F. Mirzaee, M. H. Moaiyeri, A. Jalali, O. Kavehei, High-speed full adder based on minity function and bridge style f nanoscale, Integration, the VLSI Journal, Volume 44, Issue 3, June 2011, Pages [2] K. Navi, A. Momeni, F. Sharifi, and P. Keshavarzian. Two novel ultra high speed carbon nanotube Full-Adder cells. IEICE Electronics Express 6, no. 19 (2009): [3] L. Amarú, P. E. Gaillardon, J. Zhang and G. De Micheli, "Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transists," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 10, pp , Oct [4] Chip-Hong Chang, Jiangmin Gu and Mingyan Zhang, "A review of 0.18-/spl mu/m full adder perfmances f tree structured arithmetic circuits," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 6, pp , June [5] Srivastava, A.; Srinivasan, C., " design using reconfigurable logic," Circuits and Systems, MWSCAS The th Midwest Symposium on, vol.2, no., pp.ii-663,ii-666 vol.2, 4-7 Aug [6] Paul Metzgen, A high perfmance 32-bit f programmable logic, In Proceedings of the ACM/SIGDA 12th international symposium on Field programmable gate arrays (FPGA '04). ACM, pp , New Yk, NY, USA,2004. [7] Matsunaga, Shoun, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Haruhiro Hasegawa, Tetsuo Endoh, Hideo Ohno, and Takahiro Hanyu. "Fabrication of a nonvolatile full adder based on logic-in-memy architecture using magnetic tunnel junctions." Applied Physics Express 1, no. 9 (2008): [8] Q. An, L. Su, J. O. Klein, S. Le Beux, I. O'Conn and W. Zhao, "Full-adder circuit design based on all-spin logic device," Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH 15), Boston, MA, 2015, pp

5 Floating Point Architecture Name Device Datapath width (bits) #bits in operands Time f Operation Design Type Adder M ult ipl ier Flo atin g Poi nt ITRS Node (nm) Area (µm 2 ) Model of Chip used Energy/Power Consumption (µ W) else indicate low Full Adder Based On All Spin Logic Device 2015 #26 All-Spin Logic 1.2 ps 0.69 µm Full Adder Using Power-Gated Differential Logic Style Based On Double Gating 2013 #15 Double Gate FET 8 bit operands Double Gated Controllable Polarity Transists 171 ps 2.86 µm High Speed Full Adder F Nanoscale 2011 #10 5 bit operands Bridge Style Based On Minity Carriers 32 ps um Carbon Nano-Tube High Speed Full Adder Design 2009 #11 Nano- CNFET (Carbon Nano-tube) ps 0.18 µm 3.41 Non-Volatile Full Adder Using Magnetic Tunnel Junctions 2008 #25 MOS & MTJ Magnetic Tunnel Junctions And Logic-In-Memy 219 ps 0.18 µm um Hybrid Adder Cell Review 2005 #18 Tree Structured Arithmetic Circuits 231 ps 0.18 um um High Perfmance 32-Bit f Programmable Logic 2004 #24 32 bit operands Apex 20KE Logic Element 8100 ps Apex 20KE low Using Reconfigurable Logic 2002 #21 4 bit operands Multi Input Floating Gate N-Mosfet Add: ps 1.2 µm 500 4