Design of High performance and Low Power 16T Full Adder Cells for Subthreshold Voltage Technology

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1 Design of igh performance and Low Power 16T ull dder Cells for Subthreshold Voltage Technology Ebrahim Pakniyat, Seyyed Reza Talebiyan bstract This paper presents two new structures of 1-bit full adder. It compares full adder sub-circuits and two proposed full adder circuits with common circuits in terms of propagation delay, power consumption, PDP, and P 2 DP in subthreshold voltage technology. SPICE simulations show that all the proposed adders are improved significantly in PDP and P 2 DP parameters. The full adder structures are compared in 260 (mv) voltage source. Keywords 1-bit adder, subthreshold voltage technology, propagation delay, power consumption, performance. I. INTRODUCTION DDERS are usually the most common cells used in digital systems. or instance, these circuits may be applied in rithmetic circuits and DSP systems. Power consumption and Delay time are two important parameters that must be decreased simultaneously. Power consumption is important more than Delay time, specially for portable devices. Designing adder circuits in subthreshold voltage is a suitable method for considerable reduction of power consumption [1]. In designing circuits at subthreshold voltage, a source voltage should reduce gradually as much as the threshold voltage. Power reduces considerably in the implemented circuits merely through the subthreshold current, which is achieved by correct regulation of circuit voltage source (V dd ) lower or equal to the threshold voltage (V th ). The current of transistors at subthreshold voltage is related exponentially to gate voltage, which reduces power consumption exponentially and increases delay in the circuit [1]. Consequently, a VLSI designer should use a kind of trade-off between Delay time and Power consumption. comparison can be made with respect to circuits PDP to compensate for the parameters. In fact, this article aim at examining performance of these structures using supply voltage reduction. Of course, this paper defined P 2 DP for making a better comparison and showing power consumption importance at low voltages. Section 2 introduces design of full adders. Section 3 demonstrates circuits of the E. Pakniyat is with the Electrical Engineering Department, Imam Reza (S) International University, Mashhad, Iran (corresponding author to provide phone: ; e.pakniyat@ imamreza.ac.ir). S. R. Talebiyan, is with the Electrical Engineering Department, Imam Reza (S) International University, Mashhad, Iran ( talebiyan@imamreza.ac.ir). three full adder modules. Section discusses simulation to select a superior structure and to present the results. Section 5 presents an overall conclusion on the activities performed in this paper. II. DESIN ULL DDER igure (1) shows the diagram of an XOR-XNOR-based 1-bit full adder. The circuit consists of three major modules. Since the modules may be implemented using various methods and logics, a full adder circuit can be designed using different forms and logics. In this figure, and are the inputs, C in is the carry input, and Sum is total and C out is the output carry. Expressions (1) and (2) present the relationship between the inputs and outputs [2]. S = C in (1) C =. + C. + C. (2) out in in The oolean expression in (1) and (2) may be arranged by the following expressions. = (3) Sum= C =.C +.C () out in in in C =.+C. (5) in Expressions () and (5) show, and its complement are the preliminary variables for Sum and C out, and should be produced in the module I, which are used in module II with C in for creating C out. Module III was used for producing C out using,,, and C in outputs [3]. ccording to the study of all full adders at subthreshold voltages, attempts were made here not to use NOT gates as much as possible to reduce power consumption whose major factor at low voltages is leakage power. Therefore, the circuits are used for module I, which create and signals simultaneously without needing a NOT gate. NOT gate usually need for producing a signal in XOR-XOR-based or XNOR-XNOR-based adder structures, at the following discusses XOR-XNOR-based adders. ISN:

2 ig. 1 general form of XOR XNOR-based full adder [2]. Sum and Carry outputs are produced using expressions () and (5) in all the XOR-XNOR-based adders. In this full adder, module I includes an XOR-XNOR circuit that generates and signals. Modules II and III include, 2-to-1 multiplexers with select lines of and, which generate sum and carry outputs, respectively. Simultaneous generation of and signals in full adders is important as they drive select lines of output stage of multiplexers. In another case (non-simultaneous and ), there may be glitches and unnecessary power dissipation may occur. The final outputs cannot be generated until these intermediate signals are available from module I. t section III discusses the circuits that have presented for the three full adder s modules. III. 2ULL DDER UILDIN LOCKS XOR and XNOR gates play a crucial role in different circuits, especially computational circuits and their optimal design improves efficiency of the circuits. ccording to the importance of designing and manufacturing full adders, it is necessary to discuss XOR and XNOR circuits design because they have been considered as the most fundamental element in designing this level of circuits. Simultaneous generation of XOR and XNOR has been used recently for module I extensively [, 5]. This feature is extremely favorable as output signals are generated in the module for driving select lines of a multiplexer in a full adder. igure (3) shows all the circuits that have been designed already for module I. igure () shows some frequently used circuits that have been presented already for module II. The circuits necessarily perform XOR or XNOR and they can be used in adder module I; however, they cannot have an appropriate performance in that module. igure (2) shows the 2-to-1 multiplexer circuit for module III. Output of the module can be expressed as expression (5). C D E ig. 3 circuit for module I [2] C E D J I ig. 2 circuit for module III [2] ig. circuit for module II ISN:

3 IV. SPICE SIMULTION ND RESULTS SPICE and 90 nm PTM library were employed here for performing simulations. V DD =1.2V was used for nominal value of the voltage source. The results were presented for module I and module II in voltage sources of V DD =220mV and V DD =310mV, respectively. V DD =260mV voltage source was used for comparing the full adders. Input and output buffers were used for all inputs and outputs to simulate a real environment. igure (5) shows the test structure for general simulation and size of transistors in each buffer. Size of transistors of these buffers is selected in a way that there is sufficient expected signal distortion in a real circuit. Inputs of a 1-bit full adder (,, and C in ) may change into 56 different modes. That is, three inputs of a 1-bit adder may represent eight binary figures as "000" to "111". Each eight binary figures ("000" to "111") should spring into all figures except itself. Therefore, there are seven springs for each eight binary figures. Consequently, all possible mode changes equal 7=56. This method was used for simulation of all modules. Performances of the full adder circuits and the proposed modules were evaluated in terms of the worst delay mode, power consumption, PDP, P 2 DP, in 1Mz frequency. The delay is calculated from 50% of the input voltage level to 50% of the output voltage level obtained from all the rising and falling output transitions. In order to calculate the delay in the worst condition, all the 56 modes should be examined to measure the delay of all output mode changes (C out and Sum) and introduce the biggest delay as the worst delay [2]. To have an identical comparison, all full adder circuits and simulated blocks were sized with the optimal size of the transistor Table 2. Module ІI SPICE simulation results at 90nm,V DD =310mV. Circui No. Power Delay PDP 2 ) t of (nw) (ns (aj) C D E ig. 5 simulation test bench Tables (1) and (2) show the simulation results related to studying the circuits shown for module I and module II, such as of delay, power consumption, PDP, and P 2 DP. Table 1. Module І SPICE simulation results at 90nm, V DD =220mV Circui No. Power Delay(nS) PDP 2 t of (nw) (aj) Xor Xnor C D E ig. 6 Proposed 1bit-full adder circuits, (. Proposed Circuit-1,. Proposed Circuit-2). I ISN:

4 J Table 3. ull adder SPICE simulation results at 90nm, V DD =260mV ull dder No. Power Delay(nS) PDP 2 of (nw) (aj) Sum Cout 1T CMOS ybrid CMOS ybrid PSC DPL T CPL SRCPL ull dder in [2] ull dder in [] ull dder in [7] ull dder in [6] Proposed Circuit Proposed Circuit ig. 9 Simulation results of P 2 DP for the compared full adders ig. 10 Simulation results of Power consumption for the compared full adders ig. 7 Simulation results of Delay for the compared full adders The results show that circuits and is the superior structures of module I, and J circuits are the superior structures for module II. igure (6) shows the two new structures of full adders, which were designed using the modules. Table (3) shows the simulation results of the common full adders and the two proposed full adders such as number of transistors, delay, power consumption, PDP and P 2 DP. igures (7) to (10) exhibit a comparison of Table (3) results by a diagram. ig. Simulation results of PDP for the compared full adders V. CONCLUSION This paper presents two new full-adder circuits suitable for subthreshold voltage technology. These new structure are obtained by selection of the best circuits of module I & module II (the basic building blocks of full-adder circuit). These new circuits show 11.2% and 7.05% improvements in PDP at worst case mode. REERENCES [1] V. Sharma and S. Kumar, "Low-Power 1-bit CMOS ull dder Using Subthreshold Conduction Region, "International Journal of Scientific & Engineering Research, vol. 2, [2] S. oel,. Kumar, and M.. ayoumi, "Design of Robust, Energy- Efficient ull dders for Deep-Submicometer Design Using ybrid- CMOS Logic Style." Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 1, pp , ISN:

5 [3] V. Moalemi and.fzali-kusha, "Subthreshold 1-it ull dder Cells in sub-100 nm Technologies," in VLSI, ISVLSI '07. IEEE Computer Society nnual Symposium on, pp , [] D. Radhakrishnan, "Low-voltage low-power CMOS full adder," Circuits, Devices and Systems, IEE Proceedings, vol. 1, pp. 19-2, [5] Z. Mingyan,. Jiangmin, and C. Chip-ong, " novel hybrid pass logic with static CMOS output drive full-adder cell, "in Circuit and Systems, ISCS '03. Proceedings of the 2003 international Symposium on, vol. 5, pp. V-317-V-320, [6] M. garwal, N. grawal, and M.. lam, " new design of low power high speed hybrid CMOS full adder," in Signal Processing and Integrated Networks (SPIN), 201 International Conference on, 201, pp [7] C. Eng Sue, P. Myint Wai, and. Wang Ling, "Ultra low-power fulladder for biomedical applications," in Electron Devices and Solid-State Circuits, EDSSC IEEE International Conference of, 2009, pp [] Y. Phuong Thi, N.. Z. bidin, and.. hazali, "Performance analysis of full adder () cells," in Computers & Informatics (ISCI), 2011 IEEE Symposium on, 2011, pp [9] Omid Kavehei, Mostafa Rahimi zghadi, Keivan Navi, mir-pasha Mirbaha, Design of Robust and igh-performance 1-it CMOS ull dder for Nanometer Design, IEEE Computer Society nnual Symposium on VLSI. (ISVLSI), pp , Montpellier, rance, pril 200. [10] Chip-ong Chang, Jiangmin u, Mingyan Zhang, Review of 0.1- μm ull dder Performances for Tree Structured rithmetic Circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 6, pp , June [11] Makoto Suzuki, Norio Ohkubo, Toshinobu Shinbo, Toshiaki Yamanaka, 1.5-ns 32-b CMOS LU in Double Pass-Transistor Logic, IEEE Journal of Solid-State Circuits, Vol. 2, No. 11, pp , November [12] Jian-ei Jiang, Zhi-ang Mao, Wei-eng e, Qin Wang, New ull dder Design for Tree Structured rithmetic Circuits, IEEE 2nd International Conference on Computer Engineering and Technology. (ICCET), Vol., pp , pril [13] garwal Sundeepkumar, V. k. Pavankumar, R. Yokesh, Energy Efficient, igh Performance Circuits for rithmetic Units, IEEE 21st International Conference on VLSI Design. (VLSID), pp , Jan 200. Ebrahim Pakniyat received the.sc. degree in electronics engineering from Islamic zad University of Torbat in 2012 and the M.Sc. degree in electronics engineering from International University of Imam Reza (S), Mashhad in Seyyed Reza Talebiyan received the.sc. degree in electronics engineering from erdowsi University of Mashhad in 2000 and M.Sc. and PhD degrees in electronics engineering from Semnan University and erdowsi University of Mashhad in 2002 and 2009 respectively. Now, he is an assistant professor of Imam Reza International University. is research interests include digital circuit and system design of basic building blocks for signal processing and communication systems. ISN: