Announcements. Advanced Digital Integrated Circuits. Quiz #3 today Homework #4 posted This lecture until 4pm
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1 EE241 - Spring 2011 dvanced Digital Integrated Circuits Lecture 20: High-Performance Logic Styles nnouncements Quiz #3 today Homework #4 posted This lecture until 4pm Reading: Chapter 8 in the owhill text (by Gronowski) ackground material from Rabaey, 2 nd ed, Chapters 6,10 2 1
2 Outline Last lecture Leakage management Power gating ack bias This lecture Optimal leakage ack to design for performance 3 Optimal V DD, V Th 2
3 Optimal V DD, V Th djusting V DD, V Th trades of energy and delay We studied energy-limited design There are alternate ways for optimizing energy and delay together E.g. energy-delay product (EDP) Or E n D m, n,m > 1 5 Optimal EDP Contours Gonzalez, JSSC 8/97 6 3
4 Sizing, Supply, Threshold Optimization Reference Design: D ref (V dd max,v th ref ) Topology Inverter dder Decoder (E Lk /E Sw ) ref 0.1% 1% 10% Large variation in optimal circuit parameters V dd opt, V th opt, w opt V dd max V th max V dd min V th min Technology parameters (V dd max, V th ref ) rarely optimal 7 Result: E-D Tradeoff in an dder Energ gy (E ref ) (D min,e ref ) Energy efficient curve f (W,Vdd,Vth) -40% Reference Design (D ref,e ref ) -80% Sensitivity W Vdd Vth (D ref,e ref ) (D ref,e min ) 1 (D min,e ref ) % of energy saved without delay penalty (D ref,e min ) 40% delay improvement without energy penalty Delay (D ref ) 8 4
5 Energy-constrained delay ctive power P 2 act fcv DD f = 1/L D t p Leakage power P leak I 0 e V Th V S DD V DD Eliminate i one variable(v ibl(v Th ) and find P min (V DD ) Nose, SP-DC 00 9 Minimum energy: E Sw = 2E Lk ef Op E Op / nominal E O re ref V th -180mV 081V 0.81V max dd ref V th -95mV max 0.57V dd 0.2 nominal ref V th -140mV parallel max 0.52V pipeline dd E Leakage /E Switching Large (E Lk /E Sw ) opt Flat E Op minimum Topology dependentd E E 2 L ln K avg Lk Sw opt d Optimal designs have high leakage (E Lk /E Sw 0.5) 10 5
6 Subthreshold Optimum f = 30kHz Minimum is independent of V T Calhoun, JSSC 9/05 11 High-Performance High Performance Logic Styles 6
7 CMOS Logic Styles CMOS tradeoffs: Speed Power (energy) rea Design tradeoffs Robustness, scalability Design time Many styles: don t try to remember the names remember the principles 13 CMOS Logic Styles Complementary VDD Pass Transistor Logic C PUN OUT C LOGIC NETWORK OUT C PDN GND robust scales large and slow simple and fast not always very efficient versatile 14 7
8 CMOS Logic Styles Ratioed Logic VDD Dynamic Logic V DD LOD Out GND C PDN OUT R PDN << R LOD In 1 In 2 In 3 PDN C L GND small & fast static power Small & fastest! Noise issues Scales? 15 Pulsed Static CMOS RH Reset high RL Reset low Fast pull-up Fast pull-down Chen, Ditlow, US Pat. 5,495,188 Feb
9 PS-CMOS Evaluation and reset waves: reset is 1.5x slower 17 PS-CMOS dvantages: No dynamic nodes good noise immunity Reset delay slower than evaluation No data dependent delay (worst case gets better) No false transitions Disadvantages Width of reset wave limits logic depth Margin in design 18 9
10 Pass-Transistor Logic Pass-Transistor Logic Inputs Switch Network Out Out N transistors No static consumption Transistor implementation using NMOS 0 F = 20 10
11 Pass-Transistor Logic Families 21 Pass-Transistor Logic Performance of PTL: dvantage over CMOS in implementing XOR, MUX Disadvantage in implementing ND, OR. Datapaths, arithmetic circuits are examples of use: dders and multipliers use XOR, MUX dvantage of complementary implementation Comparisons: When a new logic family is introduced, d the examples are chosen to show its advantages; (not disadvantages). Comparison papers sometimes point to the disadvantages Full-custom design 22 11
12 Examples of PTL Styles Complementary Pass-Transistor Logic (CPL) NMOS-only pass-transistor network Transmission-gate logic NMOS+PMOS pass gates Double Pass-Transistor Logic (DPL) NMOS+PMOS network Numerous other logic families 23 Complementary Pass-Transistor Logic (CPL) Pass-Transistor Network F Complementary Pass-Transistor Network F Complementary functions Reduced number of logic levels Less transistors than CMOS Fast reduced load Complementary inputs complementary outputs V T drop several solutions 24 12
13 CPL Level restoration Yano et al, CICC 89, JSSC 4/90 25 CPL Same topology of networks Just different signal arrangements 26 13
14 CPL vs. CMOS 27 Leap Cell Library Yano et al, CICC 94, JSSC 6/96 Goal: Implement full logic functionality with small library Rely on automated design methodology 28 14
15 Various Logic Functions of the Lean Library 29 Double Pass-Transistor Logic (DPL) V DD ND/NND O O XOR/XNOR O O 30 15
16 pplications of DPL Full adder: 1.5ns 32-bit LU in 0.25m mcmos Suzuki, ISSCC 93 JSSC 11/93 31 pplications of DPL 54x54bit DPL Multiplier in 4.4ns Ohkubo, CICC 94, JSSC 5/
17 4:2 Compressor in DPL 33 dder in DPL 4-bit adder 8-bit adder 34 17
18 Domino Logic Reading Chapter 8 in the owhill text (by Gronowski) ackground material from Rabaey, 2 nd ed, Chapters 6,
19 Dynamic Logic V DD V DD M p Out M e In 1 In 2 In 3 PDN C L In 1 In 2 In 3 PUN Out M e M p C L n network p network 2 phase operation: Precharge Evaluation 37 Dynamic Gates NMOS Inverter PMOS Inverter Courtesy of IEEE Press, New York
20 Dynamic Logic dvantages: Fast Compact Need to watch out for: Power Noise margins Charge leakage Charge sharing Noise coupling Charge injection Cascading dynamic gates 39 Logical Effort In Out LE = 40 20
21 Logical Effort Out Out LE = LE = 41 Charge Leakage I Leak = (I N sub + I N diode ) (I P sub + I P diode ) Time to switch the next gate: t sw = (C DYN * V sw )/I Leak Limits the minimum frequency:f min = 1/(t sw * #phases per clk cycle) Courtesy of IEEE Press, New York
22 Compensating Leakage 43 Charge Sharing (Redistribution) V DD case 1) if V out < V Tn M p Out C L V DD = C L V out t+ C a V DD V Tn V X or M a X C L V out = V out t V DD = C a V C DD L V Tn V X = 0 M b C a case 2) if V out > V Tn M e C b C a V out = V DD C a + C L 44 22
23 Charge Sharing - Solutions V DD V DD M p M a M bl Out M p M bl Out M a M b M b M e M e (a) Static bleeder (b) Precharge of internal nodes 45 side: Dynamic Latch Courtesy of IEEE Press, New York
24 Charge Sharing, = 0 DYN precharged Charge sharing if SEL toggles Courtesy of IEEE Press, New York side: Noise in ICs Sources of noise Coupling Device coupling Capacitive coupling between wires Inductive coupling Supply line bounce Charge Injection From substrate -particles, cosmic rays Robustness of a circuit Noise margins Sensitivity to noise 48 24
25 Clock Feedthrough V DD M p Out C L M a X 2.5V M b C a overshoot M e C b out 49 Miller and ack-gate Coupling Courtesy of IEEE Press, New York
26 Capacitive Coupling Courtesy of IEEE Press, New York Capacitive Coupling Dynamic node: Static node: Courtesy of IEEE Press, New York
27 Capacitive Coupling Lateral coupling: Shielding Courtesy of IEEE Press, New York Minority Charge Injection Courtesy of IEEE Press, New York
28 Supply Noise Courtesy of IEEE Press, New York Next Lecture Design in domino logic 56 28
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