Contributions on the automatic tuning of LC networks using on-chip circuits. Paulo Márcio Moreira e Silva Radiofrequency Laboratory

Transcription

1 Contributions on the automatic tuning of LC networks using on-chip circuits Paulo Márcio Moreira e Silva Radiofrequency

2 Introduction 1 Motivation: Real world problem. Ceitec s ID earring used by the cattle. ID tag (earring).

3 Introduction 2 Motivation: Real world problem. Encapsulated Tag M Reader Tag Figure: Block diagram of an ID system emphasizing the tag and its magnetic coupling with the reader.

4 Introduction 3 C 1 R s1 M R s v s L 1 v 1 v 2 L 2 v o C 2 R L i 1 i 2 Figure: Two coupled resonatinglc networks. The impedance seen from v s can be found as: Z s = v s i 1 = R s1 + ω 2 k 2 L 1 L 2 jωl 2 +R s2 + R L. (1) 1+jωR LC 2

5 Introduction 4 v o = jωk L 1 L 2 i ( R L +jωc 2 )(jωl 2 +R s ) (2) vo [V] L 2 L L 2 C 2NC freq [khz] Figure: Frequency response of v o for different values of L 2.

6 Introduction 5 Hypothesis: It is possible to conceive novel LC network tuning systems, that minimizes the required on-chip area, to be integrated on a commercial ID chip. The folowing designs were conceived: LC tuner based on negative resistances; LC tuner based on the current of an limiter; LC parameter extractor;

7 LC tuner based on negative resistances 6 LC tuner based on negative resistances Proposed Tuning Method Proposed Architecture Negative resistance Control Results Summary Other results H(C) [db] 3 db TARGET H(C) [db] 3 db TARGET δ0 δ1 δ2 δ3 δ4 δ5 δ6 δ0 δ1 δ2 δ3 δ4 δ5 δ6

8 LC tuner based on negative resistances Proposed Tuning Method 7 L R s v in C v o Figure: EquivalentRLC circuit of the tag seen by the induced voltage v in. H(s) = v o v in (s) = 1 sc(sl+r s )+1 (3) H(s) s=jω0 = L/C R s (4)

9 LC tuner based on negative resistances Proposed Tuning Method 8 H (s) [db] db 3 db R s = R sn R s = Rsn f/f 0 Figure: H (s) considering two values of R s.

10 LC tuner based on negative resistances Proposed Tuning Method 9 Capacitance response: H(C) [db] 3 db TARGET H(C) [db] 3 db TARGET δ 0 δ 1 δ 2 δ 3 δ 4 δ 5 δ 6 Capacitance [F] (a) δ 0 δ 1 δ 2 δ 3 δ 4 δ 5 δ 6 Capacitance [F] (b) Figure: H(C) for different capacitance regions (δ) with a relatively low and high Q in (a) and (b), respectively.

11 LC tuner based on negative resistances Proposed Tuning Method 10 H(C) [db] H(C) [db] δ 0 δ 1 δ 2 δ 3 δ 4 δ 5 δ 6 Capacitance [F] 3 db TARGET Determine target level and R: choose capacitance region; use a negative resistance, that is calculated based on the chosen capacitance region; set the target voltage so that it covers the desired capacitance region when the negative resistance is enabled; δ 0 δ 1 δ 2 δ 3 δ 4 δ 5 δ 6 Capacitance [F]

12 LC tuner based on negative resistances Proposed Architecture 11 Start no LC voltage reached target? no Change capacitance & wait for the LC transient All capacitances tested? yes Increase -R yes Stop Figure: Proposed flowchart.

13 + + LC tuner based on negative resistances Proposed Architecture 12 R s V LC v in L Controller R and voltage comparator (a) V LC Counter Bank of capacitors A 1 D Q CLK Q R Start V LC Target V LC V LC (b) To Counter CLK A2 Figure: (a) Block diagram of the proposed tuner and (b) implemented voltage comparator and controller.

14 LC tuner based on negative resistances Proposed Architecture 13 I 1 = max(v in )k I 2 = wi 1 I 3 = zi 1 b 12 b 13 b 14 I T M 1 M 2 A I D1 B v in v in I D2 V DC Figure: Implemented PMOS cross-coupled pair used as an adjustable negative resistance.

15 LC tuner based on negative resistances Negative resistance Control Large signal behavior of the Cross coupled pair 14 R(Z in ) = V Diff a 1 I T (5) R(Zin) [MΩ] sim. eq. (5) V Diff [V] Figure: Equivalent resistance of the cross-coupled pair at 125 khz.

16 + C 1 LC tuner based on negative resistances Negative resistance Control 15 V DD M 3 M 4 v in +V DC i 1 i 1 i t v t M 5 M 7 M 6 v in +V DC (a) v t A I 1 A T M s1 + 2 M s2 C 2 M o V SH V SH (b) Figure: (a) Proportional voltage to current converter (b) v t peak sampler.

17 LC tuner based on negative resistances Negative resistance Control 16 CLK Cs IREF CLK CLK V SH Figure:V SH signal generation.

18 + C 1 LC tuner based on negative resistances Negative resistance Control 17 V DD M 3 M 4 i 1 i 1 i t v t M 5 M 7 M 6 v t A I 1 A T M s1 + 2 M s2 C 2 M o V SH V SH Voltage [V] v in V SH v t V T time [µs]

19 LC tuner based on negative resistances Results 18 C 0 M L 1 V DD Oscilloscope v ref L 0 V DC C b 3 Designed Integrated Circuit GND L 2 GND Off-the-shelf ID antenna M Figure: Simplified schematic of the testbench used to used to validate the integrated tuner.

20 LC tuner based on negative resistances Results 19 (a) (b) Figure: (a) Photograph of the complete testbench including the photo of the designed IC. (b) Layout of the active region of the designed IC

21 LC tuner based on negative resistances Results 20 Iavg[µA] sim. meas V Diff [V] (a) R[kΩ] sim. meas V Diff [V] (b) Figure: (a) Average current consumption versus V Diff and (b) equivalent parallel IC negative resistance.

22 LC tuner based on negative resistances Results Target Cb MSB LC tuned V [V] 2 1 LC Voltage 0 Stop Start (-R off) time [ms] Increasing LC voltage as -R increases Figure: Waveform of a complete tuning sequence of the integrated tuner.

23 LC tuner based on negative resistances Results 22 Table: Performance summary and comparison with related works. Ref. Method Technology Area (mm 2 ) Power Time for tuning Freq. This work -R 130 nm µw 500 ms 125 khz [1] Rect. Voltage 90 nm NA NA 868 MHz [2] Master Slave 0.25 µm NA = 18 mw x 1.9 GHz [3] 3-dB 0.35 µm mw 9 iterations 1.97 GHz [1] M. Stoopman, S. Keyrouz, H. J. Visser, K. Philips, and W. A. Serdijn, Co-design of a CMOS rectifier and small loop antenna for highly sensitive energy harvesters, IEEE J. Solid-State Circuits, vol. 49, pp , [2] D. Li and Y. Tsividis, A 1.9 GHz Si Active LC Filter with On-Chip Automatic Tuning, IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, vol. 47, no. 3, pp , [3] F. Bahmani, T. Serrano-Gotarredona, and E. Sanchez-Sinencio, An accurate automatic quality-factor tuning scheme for second-order LC filters, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, pp , 2007.

24 LC tuner based on negative resistances Summary 23 We proposed a novel application for the negative resistance that considerably decreases the complexity of the tuning decision circuitry; We explained with details the behavior of a cross-coupled pair using MOS transistors over a wide voltage range; We also proposed a circuit to automatically control the value of the negative resistance over different voltage levels;

25 LC tuner based on negative resistances Other results 24 Publications: Automatic LC network tuner based on negative resistances. Electronics Letters, January On-chip automatic LC tuner for ID tags based on negative resistances". Accepted by the Transaction on Circuits and Systems II: Express Briefs, October 2017.

26 LC tuner based on the limiter current 25 LC tuner based on the limiter current Introduction Results Summary At Ceitec the tag is tested very close to the reader.

27 LC tuner based on the limiter current Introduction 26 C 1 M A Integrated Blocks v s L 1 L 2 C b Limiter Variable-Gain Current Amplifier Winner take all B Reference Current Counter Controller Figure: Block diagram of the LC tuning technique based on the current of the voltage limiter.

28 LC tuner based on the limiter current Introduction 27 Start limiter current reached IRef? no Change capacitance & wait for the LC transient no All capacitances tested? yes Decrease IRef no Minimum IRef? yes Decrease WTA scale yes Stop Figure: Proposed flowchart.

29 LC tuner based on the limiter current Results 28 C 1 M VDD Integrated Blocks A i tl v s L 1 C b Limiter GND i in Variable-Gain Current Amplifier Winner take all I R B Reference Current V 1, V 2 RI 1,..., RI 6 E 0, E 1, E 2 C b1, C b2, C b3 Counter CLK Controller GND Figure: Circuit used to simulate the designed tuner and its main nets and current names.

30 LC tuner based on the limiter current Results 29 Voltage [V] Current [µa] Voltage [V] V OC time [µs] i tl i in v A I R Figure: Main signals of the tuner when I R is lower than the peak of i tl.

31 LC tuner based on the limiter current Results (a) (b) Figure: (a) Designed 2 mm x 2 mm chip and (b) layout of the proposed LC tuning system. 30

32 LC tuner based on the limiter current Results 31 v A i tl I R Voltage [V] time [µs] Current [µa] Figure: Main measured signals of the presentedlc tuner.

33 LC tuner based on the limiter current Summary 32 A novel method that has the lowest power consumption among other tuners was presented; We have shown how to decrease power consumption by scaling the aspect ratio of the transistors of the WTA; Another chip was designed (Nov-13th) without the current reference core. So we will be able to analyze the system s behavior for different current values;

34 LC parameter extractor 33 LC parameter extractor Commonly implemented self-tuned LC filters Transient behavior of LC networks Implemented System Results Summary

35 LC parameter extractor Systems that either automatic tune their LC network or measure their Q 34 Ref. Method Process Freq. Area V DD Current Time for tuning / measuring [1] MS 75-GHz SiGe Bipolar 5.5 GHz > L 1.8 V < 19 ma NA [2] MS 0.25-µm BiCMOS 1.9 GHz > L V 18 ma NA [3] 3 db 0.35-µm CMOS 2 GHz <.0725 mm V < 3.6 ma 9 it. [4] Transient x 10 khz Off chip 5 V NA = 10Q/ω0 [1] J. Rogers and C. Plett, A 5-GHz radio front-end with automatically Q-tuned notch filter and VCO, IEEE Journal of Solid-State Circuits, vol. 38, no. 9, pp , Sep [2] D. Li and Y. Tsividis, A 1.9 GHz Si active LC filter with on-chip automatic tuning, in 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), vol. 47, no. 3, 2001, pp [3] F. Bahmani, T. Serrano-Gotarredona, and E. Sánchez-Sinencio, An accurate automatic quality-factor tuning scheme for second-order LC filters, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, pp , [4] M. Zhang and N. Llaser, Exploiting Time-Domain Approach for Extremely High Q-Factor Measurement, IEEE Transactions on Instrumentation and Measurement, vol. 64, pp , 2015.

36 LC parameter extractor Transient behavior of LC networks 35 2 v s (t) + t 0 L R C + v c (t) vc [V] exp( αt) eq. (6) 1 1 exp( αt) α = ω 0.5 0/(2Q) ζ = 1/(2Q) ζ = 0.05, Q = t/τ Voltage source connected to a series RLC network after t = 0. We also see the transient response of an underdamped RLC network when the switch closes at t = 0. v c (t) = V S +e t τ (A1 e jω d +A 2 e jω d ) (6)

37 LC parameter extractor Transient behavior of LC networks 36 Supposing that v s (t) is a sinusoid: v c (t) = Aω2 sinωt+sinωt Bωcosωt A 2 ω 4 +B 2 ω 2 2Aω e τω [ t (2A 2 ω 2 +B 2 2A)sinh(θt)+B B 2 4Acosh(θt) ] (A 2 ω 4 +B 2 ω 2 2Aω 2 +1) B 2 4A where A = LC, B = RC and θ = B 2 4A/2A., (7)

38 LC parameter extractor Transient behavior of LC networks 37 vc [V] calc t τ V [V] (1+exp( αt)) calc trap. 10(1+exp( αt)) α = ω r/(2q r) t τ Cases considering a tuned LC network and a detuned one. ( ) N = 5τ(f 0 f r ) f0 = 1.6Q r 1 f r (8)

39 LC parameter extractor Implemented System 38 50Ω in C t C t L 0 C 0 C r Measurement System Start R s S r On-chip system Figure: Simplified on-chip system implemented to extract the properties of L 0, C 0 and R s.

40 LC parameter extractor Implemented System 39 On-Chip Measurement System From LC network Envelope Detector Balun Comparator EN Controller Counters To S r 2 8 Reset MUX Select Start 4 Figure: Block diagram of the designedlc-parameter-extractor system.

41 LC parameter extractor Results (Simulated) 40 50Ω in I REF V DD Designed LC parameter extactor I RA Signal Generator Testbench used to simulate the parameter extractor

42 LC parameter extractor Results (Simulated) 41 Voltage [V] Voltage [V] Voltage [V] v LC time [µs] EA v OENV v OC Figure: Complete sequence of the LC parameter extractor.

43 LC parameter extractor Results 42 (a) (b) Figure: Layout and fabricatedlc parameter extractor wirebonded on an FR-4 PCB in (a) and (b), respectively.

44 LC parameter extractor Results 43 Zin [Ω] ma 1 ma 1.5 ma 2 ma 2.5 ma freq [MHz] Figure: Measured Z in. I REF (ma) Q sim. Q meas >4000 Table:I REF and the simulated and measured unloadedq.

45 LC parameter extractor Results V [V] time [ns] start v OENV Envelope [V] Figure: Measured envelope using I REF = 3mA.

46 LC parameter extractor Systems that either automatic tune their LC network or measure their Q 45 Ref. Method Process Freq. Area V DD Current Time for tuning / measuring [1] MS 75-GHz SiGe Bipolar 5.5 GHz > L 1.8 V < 19 ma NA [2] MS 0.25-µm BiCMOS 1.9 GHz > L V 18 ma NA [3] 3 db 0.35-µm CMOS 2 GHz <.0725 mm V < 3.6 ma 9 it. [4] Transient x 10 khz Off chip 5 V NA = 10Q/ω0 LC p. ext Transient 130-nm CMOS 0.9 GHz.034 mm V 1.6 ma 2µs [1] J. Rogers and C. Plett, A 5-GHz radio front-end with automatically Q-tuned notch filter and VCO, IEEE Journal of Solid-State Circuits, vol. 38, no. 9, pp , Sep [2] D. Li and Y. Tsividis, A 1.9 GHz Si active LC filter with on-chip automatic tuning, in 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), vol. 47, no. 3, 2001, pp [3] F. Bahmani, T. Serrano-Gotarredona, and E. Sánchez-Sinencio, An accurate automatic quality-factor tuning scheme for second-order LC filters, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 54, pp , [4] M. Zhang and N. Llaser, Exploiting Time-Domain Approach for Extremely High Q-Factor Measurement, IEEE Transactions on Instrumentation and Measurement, vol. 64, pp , 2015.

47 LC parameter extractor Summary 46 We present a solution for extracting the parameters of an LC network without the need of extra inductors; With the transient modeling, we proposed a method for estimating the parameters of an LC tank (Q and the tuning); The measurements results of the prototype was shown and we have seen that the prototype is almost fully working as expected; Another version of this system was sent to fabrication (Nov-13th);

48 Conclusions 47 We can say that we designed 3 different tuners for one port devices. Method Neg Res tuner current limiter Transient LC p. extract. Table: Performance of the tuners conceived in this thesis. CMOS Process V DD I avg Time for tuning Area Frequency 130 nm 3.3 V 12µA/V 250 ms mm 2 125kHz 130 nm 3.3 V 10µA 32 ms mm 2 125kHz 130 nm 3.3 V 1.6mA > 2µs mm 2 900MHz

49 Conclusions Main contributions 48 We present two novel methods for tuning LC networks; We proposed a circuit for controlling the negative resistance of a cross-coupled pair; We show how we are able to decrease the power consumption of the LC parameter based on the limiter current. A novel LC parameter extractor, operating at 900MHz, that digitally reports the parameter of the LC network is presented.

50 Conclusions 49 Future work: In a longer term, it would be interesting to propose a digital control circuitry for the LC parameter extractor. Then, an LC filter could be programed to behave as required by the user.

51 Thank You Phone: +55(48) Web page: