Fully Integrated Low Phase Noise LC VCO. Desired Characteristics of VCOs

Transcription

1 Fully Integrated ow Phase Noise C VCO AGENDA Comparison with other types of VCOs. Analysis of two common C VCO topologies. Design procedure for the cross-coupled C VCO. Phase noise reduction techniques. Desired Characteristics of VCOs ow phase noise. Wide tuning range. ow cost (i.e. compatible with IC process). Small size. ow power consumption.

2 Comparison of various types of VCOs esonator Type C (integrated) C (discrete) Fruency ange 500 MHz 0 GHz 00 MHz GHz Quality Factor Tuning ange Wide Wide Cost Very low ow Only C and transmission line VCOs are suitable for IC process. Quartz crystal Ceramic MHz 500 MHz KHz 0 MHz Very narrow Very narrow High ow Transmission lines have higher Q but are much larger than spiral inductor. Transmission line > 00 MHz Wide Moderate Surface Acoustic Wave (SAW) 00 MHz GHz Narrow High Dielectric (DO) GHz 0 GHz About 000 Narrow Moderate Complimentary Cross-Coupled C VCOs Easy to design. M VO+ VDD M4 VO- Power efficient since bias current is shared between the two transconductors. M C VTUNE C M ESONATO C I(t) Not suitable for low-voltage design due to voltage drop of bias transistor. M5 I BIAS (a) Complimentary crosscoupled C VCO (b) Equivalent Circuit For operation in current-limited regime: 4 VO = I BIAS EQ (Ideal switching) π VO I BIAS EQ (High fruency) 4

3 Singly cross-coupled C VCO VDD By superposition: VO = I ( t) Z // jωc // jωc + jω VO+ M / C VTUNE M5 / C I BIAS VO- M C Z / / I(t) I(t) Z jω jω = // + // jωc Simplifying using the identity VO = I( t) = I π BIAS EQ ω = C (a) Singly cross-coupled C VCO (b) Equivalent Circuit Singly cross-coupled C VCO in general has poorer phase noise performance than the complimentary one. 5 Design Procedure for cross-coupled C VCO. Use design tool such as ASITIC to obtain the? model of the spiral inductor.. Convert to parallel uivalent, assuming Q>>.. Estimate VCO output swing V O. V DS5 should be chosen to be about 4 times V DS5(sat) to minimize noise up-conversion by the bias transistor. 4. Compute the bias current, assuming the resonator Q is dominated by the inductor Q. s s p P P S = P P + ω0 P ω0 PP ω0 P S = P + ω0 P P V = V I O BIAS DD V V O P TP V TN V DS5 p 6

4 Design Procedure for cross-coupled C VCO 5. Compute the W/ of the two transconductors, assuming that the negative resistance is ually divided between them, and the magnitude of the total negative resistance is ual to / of P for reliable startup. 6. Compute C to get the desired oscillation fruency. g P m = P W k' I W k' I D = P BIAS = = ω C 0 7 Design Example Problem: Design a 5.5-GHz complimentary cross-coupled C oscillator, given that S =.6nH, S =4.5, V DD =.8V, V TN =0.V, V TP =0.5V, k N =70µA/V, k P =75µA/V, and V DS5(sat) =0.7V Answer: I BIAS =.50mA, (W/) =77, (W/) =40, (W/) 5 =6, C=664.6fF Notes: The actual bias current and capacitance should be less than the calculated values, due to parasitic capacitance of the transistor. 8 4

5 Phase Noise eduction Techniques Phase noise can be reduced by:. Increasing the Q of the C tank, i.e. better design techniques for planar inductor and varactor.. Increasing the output voltage swing.. educing the effect of the bias transistor /f noise upconversion. 4. educing transistor noise. T. H. ee, and A. Hajimiri, Oscillator Phase Noise: A tutorial, IEEE J. Solid State Circuits, vol. 5, no., pp. 6-5, Mar. 000 T. H. ee, and A. Hajimiri, Design Issues in CMOS Differential C Oscillators, IEEE J. Solid State Circuits, vol. 4, no. 5, pp.77-74, May Spiral Inductor osses B Field Spiral Trace Eddy loops Inductor Current Metal trace resistance, increased at high fruency due to skin effect and current crowding effect. Parasitic capacitance between metal trace and substrate. Magnetic field coupling to the substrate, causing image current to flow in the substrate (Faraday s law). 0 5

6 High-Q Spiral Inductor Design Techniques (a) (b) imit the width of the metal conductors. Use minimum spacing in between the conductors. Do not fill the inductor up to the center. imit the area occupied by the coil. Use octagonal shape to minimize trace metal resistance. Shunt multiple metal layers to reduce trace resistance. Use pattern ground shield. Pattern Ground Shield The effectiveness of pattern ground shield is questionable. Only N+ diffusion shield shows some improvement, but only for fruency below GHz. 6

7 everse Biased p-n Junction Varactor Does not scale with technology. Have limited tuning range, typically less than ½ supply. Have relatively high parasitic series resistance. MOS Varactor Have larger capacitance/area ratio than p-njunction varactor. Have larger tuning range than p-n junction varactor. Have lower parasitic resistance than p-n junction varactor. Scale with technology. 4 7

8 Accumulation-mode Varactor Can be constructed as a pmos transistor with the D/S p+ diffusions removed, to suppress any injection of holes into the channel, thereby eliminating the formation of inversion region. Have lower parasitic resistance than a MOS varactor since electrons are the majority carriers. 5 Phase Noise Contribution of Varactor Noise appearing on the varactor terminals, will vary the CM signal which, in turn, varies the capacitance which is translated to phase noise at the VCO output. This problem can be alleviated by utilizing an array of fixed switched capacitance, in parallel with a much smaller varactor. The drawback is the on resistance of switching transistors will degrade the Q of the resonator. Another approach is to use an array of smaller varactors, with all but one discretely switched between two extremes of the varactor tuning range. 6 8

9 Tail Current Noise Suppression High fruency noise of the tail current transistor is suppressed by C flt. flt is chosen to resonate at the second harmonic, thereby preserving the high impedance at the drain of the tail current transistor. A large external inductor lf is used to degenerate the tail transistor, reducing the low fruency noise power by + jg ω. m fl An external capacitor can be used in place of the inductor, but it also provides a low impedance for the common source of the switching transistors. 7 9