University of Minnesota, Minneapolis, MN 2. Intel Corporation, Hillsboro, OR 3. Los Alamos National Laboratory, Los Alamos, NM
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1 Statistical Characterization of Radiation- Induced Pulse Waveforms and Flip-Flop Soft Errors in 14nm Tri-Gate CMOS Using a Back- Sampling Chain (BSC) Technique Saurabh Kumar 1, M. Cho 2, L. Everson 1, H. Kim 1, Q. Tang 1, P. Mazanec 1, P. Meinerzhagen 2, A. Malavasi 2, D. Lake 2, C. Tokunaga 2, H. Quinn 3, M. Khellah 2, J. Tschanz 2, S. Borkar 2, V. De 2 and C. H. Kim 1 1 University of Minnesota, Minneapolis, MN 2 Intel Corporation, Hillsboro, OR 3 Los Alamos National Laboratory, Los Alamos, NM kumar175@umn.edu This research was, in part, funded by the U.S. government. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the U.S. government Symposia on VLSI Technology and Circuits
2 Outline Motivation Back-sampling chain (BSC) technique 14nm test-chip and board design Neutron irradiation test results Strike pulse re-construction results Conclusion Slide 1
3 S Soft Error: Planar vs. Tri-Gate D G G Fin S D Charge collection Charge collection Device level soft error rate has been decreasing with scaling FIT/Mb (Log Scale) S. Lee et. al. IRPS 2015 Planar Finfet High energy neutron Alpha particle Thermal neutron Technology (nm) Slide 2
4 Scaling Impact on SER in Tri-Gate G Smaller crosssection S D Narrower path 14nm 10nm Lower SER with tri-gate scaling Taller/narrower fins, higher resistance Smaller cross-section Slide 3
5 Scaling Impact on SER in Tri-Gate Transistor density (MTr / mm 2 ) nm 32nm 22nm 14nm Year of production 10nm Supply Voltage (a.u.) Lower per-transistor SER Higher transistor count, lower VDD increased chip-level SER Challenge: Collecting statistically significant amount of data in limited beam time Slide 4
6 Logic SET vs. Sequential SEU/MBU 1 1 D Clk 1 0 Clk To slave Clk Clk Clk Combinational logic path Flop storage node VDD VDD Vnode Trip point of next stage Vnode Flipping threshold Time Time Slide 5
7 Circuit Dependencies 1 V node I strike P 1 P 2 1 For higher SER sensitivity: - I restore - I strike - C node - V sw N 1 V sw N 2 I restore C node : High V T, smaller size (N 1 ) : High flux/let (radiation parameter) : Small fan-out, device size : High V T, smaller device (P 2 ) Slide 6
8 Technique #1: Current Starved Buffers Long chain of current starved buffers: detection circuit Starved buffer chain: High sensitivity Slide 7
9 Technique #1: Current Starved Buffers SER strike V PO V PE V PO V PE V NO V NE V NO V NE Alternate starving: Lower I restore, lower V sw Analog bias knobs: Tunable resolution and sensitivity Critical charge (Qcrit, normalized) Standard chain This work 1x INV, TT, 27 C Higher sensitivity Voltage (V) Slide 8
10 Technique #2: Back-Sampling Chain SER strike V PO V PE V PO V PE V NO V NE V NO V NE N2 Later stage rising edge back-samples previous stage falling edge Stage Output # of 0's indicate original pulse width Time Slide 9
11 Example: Short vs. Long Strike Pulse Stage Output Unsampled original bits Long trail of 0's Stage Output Unsampled original bits Short trail of 0's Time Time Slide 10
12 Min. detection amplitude (normalized to VDD) Tunable Resolution and Sensitivity Sensitivity vs resolution trade-off Resolution (ps) Allows multiple resolution-sensitivity sweeps Facilitates strike pulse re-construction V PO V NO V PE V PO V PE V NE V NO V NE N2 Slide 11
13 Back-Sampling Chain (BSC) Array Buff In Scan Out Q D Q D Q D D Q D Q D Q Q D Q D Q D D Q D Q D Q Unit Cell C1 Q D Q D Q D Scan In D Q D Q D Q Buff Out Q D Q D Q D D Q D Q D Q Slide 12
14 SER Test Board Fabricated Board Beam diameter = 3 inches 3x3 SER test-chips fit within beam area FPGA: JTAG support for automated control 15.3 million BSC stages per board Slide 13
15 LANL Neutron Irradiation Test 10 stacked boards with 90 test-chips in parallel irradiated under neutron beam at Los Alamos National Laboratory (LANL) Slide 14
16 Neutron Beam Parameters Source: Los Alamos National Laboratory Neutron beam specs Avg. energy spectrum range: MeV Avg. neutron flux: ~ 4.2x10 4 neutrons/cm 2 /s Slide 15
17 Neutron Test Data: SET A strike on buffer node induces SET FF Data = FF Data = Slide 16
18 Neutron Test Data: SEU/ MBU A strike on flop storage node induces SEU/ MBU FF Data = SEU FF Data = MBU Slide 17
19 Strike Pulse Width Distribution 1.E+05 Pulse count 1.E+04 1.E+03 1.E+02 Voltage Time 0.40V V DD, 0.30V V GS 0.50V V DD, 0.30V V GS 0.60V V DD, 0.30V V GS 0.6V Sampling 0.5V 0.4V cut-offs 1.E Pulse width (ns) With lower VDD, sampling cut-off drops and wider SET pulses are sampled Q crit decreases with lower VDD, increasing SER Slide 18
20 Strike Pulse Width Distribution 1.E+05 Pulse count 1.E+04 1.E+03 1.E+02 Voltage 0.40V V DD, 0.20V V GS 0.40V V DD, 0.25V V GS 0.40V V DD, 0.30V V GS Time 0.30V V GS 0.25V V GS Sampling 0.20V V GS cut-offs 1.E Pulse width (ns) With stronger starving (lower V GS ), sensitivity increases and sampling threshold drops, sampling wider SET pulses Slide 19
21 SET Pulse Re-construction Slide 20
22 SET Pulse Re-construction Slide 21
23 SET Pulse Re-construction FWHM: Full width at half maximum Slide 22
24 SET Pulse Re-construction FWHM: Full width at half maximum Higher amplitude = shorter pulse width (lower FWHM) To our knowledge, this is the first time individual strike pulses are reconstructed Slide 23
25 SET Pulse Re-construction 0.5 VDD=0.5V VDD=0.4V Voltage (V) FWHM AVG : 218ps Amplitude AVG : 0.42 FWHM AVG : 222 ps Amplitude AVG : Time (ns) Time (ns) Lower VDD: pulse amplitude, pulse width Slide 24
26 Comparison with Prior Art To TDC TDC based circuit [1] Pulse shrinking [2] This work Unit cell layout Irregular, not easily scalable Regular, scalable Regular, scalable Sensitivity tuning Fixed by design Fixed by design Variable using bias knobs * Resolution > 30ps > 1ps > 1.3ps Q crit sensitivity * 1x 0.6x 9x * Results reproduced in 14nm process [1] T. D. Loveless et. al. TNS 2012 [2] J. Furuta et.al. IRPS 2011 Slide 25
27 Flip-Flop SEU/MBU Failure In Time (normalized) FIT: # of SER per flop per billion hours Cross-section (normalized) bit 4-bit 3-bit bit 1-bit VDD (V) VDD (V) SER exponentially increases with lower VDD At lower VDDs, MBU become more dominant Slide 26
28 Conclusion BSC chain technique proposed with 9x lower Q crit and picosecond range resolution BSC circuit detects SET, SEU, and MBU 14nm test-chip irradiated under neutron beam Individual strike pulses re-constructed based on neutron irradiation data Next step: SER model framework development Slide 27
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