Random telegraph signal noise simulation of decanano MOSFETs subject to atomic scale structure variation
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1 Superlattices and Microstructures 34 (2003) Random telegraph signal noise simulation of decanano MOSFETs subject to atomic scale structure variation Angelica Lee, Andrew R. Brown, Asen Asenov, Scott Roy Device Modelling Group, Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow G12 8LT, UK Available online 16 April 2004 Abstract As MOSFETs shrink into the decanano regime it is predicted that random telegraph signals (RTS), resulting from trapping events in defect states near the Si/SiO 2 interface, will significantly affect analogue and digital circuit performance. At these same scales, intrinsic parameter fluctuations introduced by atomic differences between devices will also be significant. In this work, a methodology based on 3D simulation is developed which can correctly model RTS noise in the time and frequency domain in the presence of random discrete dopants. The approach is illustrated with results obtained for nm devices. We find that atomicity can significantly increase RTS magnitude in devices with particular doping configurations, and ensemble average RTS effects vary markedly from those predicted on an assumption of continuous doping Elsevier Ltd. All rights reserved. Keywords: MOSFET; Atomistic; Random telegraph signals; Noise; Simulation 1. Introduction The low frequency noise performance of silicon MOSFETs continues to be a subject of interest to both academia and industry. As the channel length of mass produced devices continues to shrink into the decanano regime, it becomes a significant factor in analogue circuitperformance [1], dynamicrandomaccess memoryoperation [2], andwill eventually impact critically upon the reliability of digital logic. Random telegraph signals (RTS) of Lorentzian power spectrum, resulting from the capture and emission of charge from Corresponding author. Tel.: ; fax: address: s.roy@elec.gla.ac.uk (S. Roy) /$ - see front matter 2004 Elsevier Ltd. All rights reserved. doi: /j.spmi
2 294 A. Lee etal. / Superlattices and Microstructures 34 (2003) Fig. 1. Dependence of relative RTS amplitude on drain current (at low drain voltage, V D = 10 mv) for a set of square MOSFETs of differing size. Trap is placed for maximum RTS amplitude in continuously doped device. defect states near the Si/SiO 2 interface and an associated modulation in carrier density and mobility, dominate the low frequency noise performance of small MOSFETs around and below threshold [3]. RTS with amplitudes larger than 60% have been reported for devices at room temperature [4]. There have been a number of recently proposed models describing the nature of RTS events and 1/f noise which can usefully be described as a superposition of Lorentzian spectra in MOSFETs [4 6]. Another category of effects which are of critical concern as device dimensions shrink, are those arising from the granularity of charge and matter. Among them, threshold voltage and current fluctuations between nominally identical devices due to random dopant configurations [7] have been much studied recently. Of particular interest to this work are the consequences of such atomistic effects on the RTS noise in a single decanano device, or ensembles of decanano devices. We consider how the magnitude and timing parameters of RTS drain current noise are altered when random discrete dopants are taken into account in 3D MOSFET simulations instead of assuming continuous doping. An extension to the simulator which can model RTS noise in the time domain has also been developed. 2. Simulation of RTS amplitude Our approach, described in detail in [5], uses a 3D drift-diffusion simulator which appropriately accounts for the electrostatic effects associated with random discrete dopants, and is well suited to describe RTS in the sub-threshold regime. Fig. 1 illustrates RTS amplitudes obtained from this simulator for a set of devices with dimensions from nm down to nm, assuming continuous doping and a single electron trapped in the centre of the channel at the Si/SiO 2 interface where it will have the maximal effect. As can
3 A.Lee et al. / Superlattices and Microstructures 34 (2003) Fig. 2. Potential barrier between source and drain in a nm MOSFET showing the effect of a single unscreened trapped charge at the interface. be seen, the nominal drain current drops by 5% 40% on activation of the trap in the subthreshold regime depending on device size, although the magnitude of the RTS signal becomes much reduced at higher gate voltages for both long and short channel devices due to screening. Note that all these results are taken at low drain voltage (V D = 10 mv) to remain within the regime of applicability of the drift-diffusion model. Fig. 2 plots the potential across one of these devices, clearly showing the potential barrier of the channel in subthreshold, and indicating how that barrier is augmented by trap activation. The mesh size is chosen to resolve well the long range part of the Coulomb potential which determines the mobile charge exclusion region in sub-threshold.from Fig. 2 it is qualitatively obvious that if thetrap is found nearer to the source or drain junction its effect on sub-threshold current will be markedly reduced, either because in the source/drain depletion regions the trap is no longer at the peak of the potential barrier, or because further into the source/drain regions it is heavily screened. In addition, a trap found offset from the centre of the channel width will leavethe opposite region of the channel augmented by a lower Coulomb field, ameliorating the overall channel RTS current reduction. These results are shown quantitatively in Fig. 3, which maps the fractional RTS magnitude as a function of trap position in the channel. An advantage of our 3D approach is that RTS amplitudes can be obtained in the presence of the fluctuating channel potentials found in realistic MOSFETs subject to discrete random dopants. Fig. 4 shows three different discrete profiles (ordered by increasing threshold voltage from left to right) for nm devices, and the positional dependence of RTS amplitude in each configuration. In the middleplot, most of the dopants within 3 nm of the Si/SiO 2 interface are found to be to the north side of the channel, raising the potential in this area. For any given gate voltage, current will flow most easily from source to drain along the lower potential southern region of the channel. Trap activation in this region will have greatest effect on the overall current flow. In the left hand plot most dopants
4 296 A. Lee etal. / Superlattices and Microstructures 34 (2003) Fig. 3. Positional dependence of the magnitude of RTS fluctuations in the drain current of a nm MOSFET with an assumed continuous spread of doping, as a function of trap position in the channel region. Fig. 4. Positional dependence of the magnitude of RTS fluctuations in drain current caused by a single trap/de-trap event in one of three nm MOSFETs subject to discrete random dopants in the channel region. Dopant position saturation indicates whether they fall within the 1st, 2nd or 3rd nm from the Si/SiO 2 interface. are again found to the north of the channel, with one additional dopant in the south producing a narrow percolation path. Trap activation in this path gives RTS amplitudes of up to 70%. In the right hand plot, in addition toahigher dopant density near the Si/SiO 2 interface raising V T,the dopants are more uniformly distributed across the width of the channel, and the positional dependence of the RTS fluctuations more closely approaches that of a continuously doped device. Fig. 5 shows the mean positional dependence of RTS amplitude for an ensemble of 100 atomistic devices. Although a particular atomistic device may exhibit RTS amplitudes over 70%, approaching twice that of devices with a continuous dopant spread, the ensemble average has approximately the same peak value as that of an ostensibly continuous device.
5 A.Lee et al. / Superlattices and Microstructures 34 (2003) Fig. 5. Average positional dependence of the magnitude of RTS fluctuations in the drain current of an ensemble of nm MOSFETs subject to discrete random dopants, as afunction of trap position in the channel region. However the formation of percolation paths in the presence of atomicity means that trap activation at any point along the width of the channel may produce strong fractional RTS amplitudes, a distinct feature resulting from the consideration of more realistic devices. 3. Time domain simulation Having calculated the distribution of the RTS amplitudes, the simulator may be extended to obtain time domain results (and hence power spectral densities of noise in ultra-small MOSFETs in the sub-threshold regime) once statistics of trap capture and emission times, τ c, τ e,areknown. Both are thermally activated processes, and so τ c,for example is given by [8], τ c = exp( E c/k B T ) nνσ o where E c is the activation energy, n the inversion layer charge density, and for low V D, ν and T are the average thermal electron velocity and the lattice temperature. E c is a function of the Si conduction band energy at the interface, and the trap energy, and will vary with V G and the depth of the trap in the oxide layer (we assume a random depth distribution). Sample data for capture and emission times in this work are obtained [8], with specific τ c and τ e requiring recalculation for each atomistic configuration and bias conditions. The methodologyis overviewedin Fig. 6.The top graph shows the probability of a given RTS amplitude in an ensemble of nm MOSFETs. The right hand cartoon indicates the introduction of specific trap/de-trap timing by Monte Carlo. The lower graph in Fig. 6 is part of a typical simulation combining both amplitude and timing. It is a small segment
6 298 A. Lee etal. / Superlattices and Microstructures 34 (2003) Fig. 6. Methodology overview for extracting time domain results from atomistic device simulations (where RTS amplitudes may be obtained as a function of trap position top right graph from [5]) and trap/de-trap statistics (as a function of trap energy level, and electron density). taken from one member of the ensemble near threshold at low drain voltage, V G = 0.5 V, V D = 0.01 V, and clearly indicates the effect of two active traps in the device. From the full trace in this case over a simulation time period of >400 s the power spectral density of Fig. 7 is obtained. (The black trace calculates the power spectral density down to 0.01 Hz, the central trace re-samples the time domain data in the frequency range of interest to better characterize the noise.) As expected, the noise shows typical 1/f behaviour, with a characteristic frequency, f c = 1 τ c + 1 τ e around 20 Hz, agreeing with simulation capture and emission times of approximately 100 ms in this case. It should be noted [3], that although the power spectral density usefully characterizes aspects of the data, time domain traces are always retained, both for further simulation in circuit models, but also because, for instance, thepower spectral density of a single trap is proportional to, PSD β 1 + β 2 f c f 2 c + f 2 where β = τ c τ e so it is impossible toconfirm, solely from the power spectral density, the τ c /τ e ratio.
7 A.Lee et al. / Superlattices and Microstructures 34 (2003) Fig. 7. Power spectral density obtained from time domain simulation of nm MOSFET in the subthreshold regime (V D = 10 mv, V G = 500 mv) containing two active traps with corner frequencies of approximately 20 Hz and 100 Hz. 4. Conclusions We have developed a methodology and corresponding simulation tools which can model both the magnitude and timing of RTS noise in decanano MOSFETs subject to atomic scale variations in dopant positions. The approach has been illustrated simulating the noise in a nm devices. We have shown that the source/drain percolation paths associated with random discrete dopants in real MOSFETs have a strong effect on the positional dependence of the magnitude of RTS fluctuations in device drain current. Acknowledgements This work was carried out under an Engineering and Physical Sciences Research Council grant GR/R References [1] M.J.Kirton, M.J.Uren,Noise in solid state microstructures: a new perspective on individual defects, interface states and low frequency (1/ f ) noise?, Adv. in Phys. 38 (1989) [2] P.J. Restle, J.W. Park, B.F. Lloyd, DRAM variable retention time, IEDM Tech. Dig. (1992) [3] A.P. van der Wel, E.A.M. Klumperink, L.K.J. Vandamme, B. Nauta, Modeling random telegraph noise under switched bias conditions using cyclostationary RTS noise, IEEE Trans. Electron Dev. 50 (2003) [4] H.M. Bu, Y. Shi et al., Impact of the device scaling on the low-frequency noise in n-mosfets, Appl. Phys. A71(2000) [5] A. Asenov, R. Balasubramanian, A.R. Brown, J.H. Davies, RTS amplitude in decananometer MOSFETs: 3-D simulation study, IEEE Trans. Electron Dev. 50 (2003)
8 300 A. Lee etal. / Superlattices and Microstructures 34 (2003) [6] F.-C. Hou, G. Bosman, M.E. Law, Simulation of oxide trapping noise in submicron n-channel MOSFETs, IEEE Trans. Electron Dev. 50 (2003) [7] A. Asenov, Random dopant induced threshold voltage lowering and fluctuations in sub 50 nm MOSFETs: a 3D atomistic simulation study, Nanotechnology 10 (1999) [8] Z. Shi, J.-P. Miéville, M. Dutoit, Random telegraph signals in deep submicron n-mosfets, IEEE Trans. Electron Dev. 41 (1994)
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