Tradeoffs and Optimization in Analog CMOS Design
|
|
- Elmer Pope
- 6 years ago
- Views:
Transcription
1 Tradeoffs and Optimization in Analog CMOS Design David M. Binkley University of North Carolina at Charlotte, USA A John Wiley & Sons, Ltd., Publication
2 Contents Foreword Preface Acknowledgmerits List of Symbols and Abbreviations xvii xxi xxiii xxv 1 Introduction Importance of Tradeoffs and Optimization in Analog CMOS Design Industry Designers and University Students as Readers Organization and Overview of Book Füll or Selective Reading of Book Example Technologies and Technology Extensions Limitations of the Methods Disclaimer 7 PART I MOS Device Performance, Tradeoffs and Optimization for Analog CMOS Design 9 2 MOS Design from Weak through Strong Inversion Introduction MOS Design Complexity Compared to Bipolar Design Bipolar Transistor Collector Current and Transconductance MOS Drain Current and Transconductance In Weak Inversion In Strong Inversion without Velocity Saturation Effects In Strong Inversion with Velocity Saturation Effects In Moderate Inversion and All Regions of Operation MOS Drain-Source Conductance Analog CMOS Electronic Design Automation Tools and Design Methods Electronic Design Automation Tools Design Methods Previous Application of Design Methods Presented in this Book 29 References 30 3 MOS Performance versus Drain Current, Inversion Coefficient, and Channel Length Introduction Advantages of Selecting Drain Current, Inversion Coefficient, and Channel Length in Analog CMOS Design 34
3 viii CONTENTS Optimizing Drain Current, Inversion Coefficient, and Channel Length Separately Design in Moderate Inversion Design Inclusive of Velocity Saturation Effects Design with Technology Independence Simple Predictions of Performance and Trends Minimizing Iterative Computer Simulations - "PreSPICE" Guidance Observing Performance Tradeoffs - The MOSFET Operating Plane Cross-Checking with Computer Simulation MOS Models Process Parameters for Example Processes Calculation of Composite Process Parameters DC, Small-Signal, and Intrinsic Gate Capacitance Parameters Flicker Noise and Local-Area DC Mismatch Parameters Gate-Overlap and Drain-Body Capacitance Parameters Temperature Parameters Substrate Factor and Inversion Coefficient Substrate Factor Inversion Coefficient Traditional inversion coefficient Fixed-normalized inversion coefficient Using the fixed-normalized inversion coefficient in design Regions and subregions of inversion Temperature Effects Bandgap Energy, Thermal Voltage, and Substrate Factor Mobility, Transconductance Factor, and Technology Current Inversion Coefficient Threshold Voltage Design Considerations Sizing Relationships Shape Factor Channel Width Gate Area and Silicon Cost Drain Current and Bias Voltages Drain Current Without small-geometry effects With velocity Saturation effects With VFMR effects With velocity Saturation and VFMR effects The equivalent velocity Saturation voltage Predicted and measured values The extrapolated threshold voltage Effective Gate-Source Voltage Without small-geometry effects With velocity Saturation and VFMR effects\ Predicted and measured values Summary of trends Drain-Source Saturation Voltage Physical versus circuit defmition Without small-geometry effects With velocity Saturation effects 92
4 CONTENTS ix Predicted and measured values Summary of trends Small-Signal Parameters and Intrinsic Voltage Gain Small-Signal Model and its Application Transconductance Without small-geometry effects With velocity Saturation and VFMR effects Predicted and measured values Summary of trends Universal g m /I D characteristic in CMOS technologies Distortion Body-Effect Transconductance and Relationship to Substrate Factor Substrate factor Body-effect transconductance Predicted and measured values Summary of trends Drain Conductance 130 ^ Due to Channel length modulation DuetoDIBL Due to hot-electron effects Impact of increase near V DSsal Measured values Summary of trends Intrinsic Voltage Gain Capacitances and Bandwidth Gate-Oxide Capacitance Intrinsic Gate Capacitances Extrinsic Gate-Overlap Capacitances Drain-Body and Source-Body Junction Capacitances Intrinsic Drain-Body and Source-Body Capacitances Intrinsic Bandwidth Extrinsic and Diode-Connected Bandwidths Noise Thermal Noise in the Ohmic Region Thermal Noise in the Saturation Region Without small-geometry effects With small-geometry effects Summary of drain-referred and gate-referred thermal noise Flicker Noise Carrier density fluctuation model Carrier mobility fluctuation model Unified, carrier density, correlated mobility fluctuation model Flicker-noise prediction from flicker-noise factors Reported flicker-noise factors and trends Measured and predicted flicker noise Summary of gate-referred and drain-referred flicker noise Flicker-noise corner frequency Gate, Substrate, and Source Resistance Thermal Noise Channel Avalanche Noise Induced Gate Noise Current Gate Leakage Noise Current 231
5 CONTENTS 3.11 Mismatch Local-Area DC Mismatch Modeling Reported mismatch factors and trends Edge effects and other model limitations Calculating gate-source voltage and drain current mismatch Threshold-voltage mismatch increase for non-zero V SB Threshold-voltage dominance of mismatch Summary of gate-source voltage and drain current mismatch Distance DC Mismatch Modeling Reported mismatch factors and trends Gate-source voltage and drain current mismatch Threshold-voltage dominance of mismatch Critical spacing for comparable distance and local-area mismatch DC Mismatch Effects on Circuit Performance Bandwidth, power, and accuracy tradeoffs in current-mode circuits Bandwidth, power, and accuracy tradeoffs in voltage-mode circuits Tirning skew in digital circuits Small-Signal Parameter and Capacitance Mismatch Transconductance mismatch Drain-source conductance mismatch Mismatch effects on circuit Performance Leakage Current Gate Leakage Current and Conductance Gate current Gate conductance Gate Leakage Current Effects on Circuit Performance Minimum frequency of Operation Intrinsic current gain Discharge of capacitances Noise Mismatch Summary of tradeoffs Drain-Body and Source-Body Leakage Current Subthreshold Drain Leakage Current 282 References 283 Tradeoffs in MOS Performance, and Design of Differential Pairs and Current Mirrors Introduction Performance Trends Exploring Drain Current, Inversion Coefficient, and Channel Length Separately Trends as Inversion Coefficient Increases Trends as Channel Length Increases Trends as Drain Current Increases Performance Tradeoffs Overview - The MOSFET Operating Plane Region and Level of Inversion - The Inversion Coefficient as a Number Line 304
6 CONTENTS xi Tradeoffs Common to All Devices Channel width and gate area Intrinsic gate capacitance and drain-body capacitance Effective gate-source voltage and drain-source Saturation voltage Transconductance efficiency and Early voltage Intrinsic voltage gain and bandwidth Tradeoffs Specific to Differential-Pair Devices Transconductance distortion Intrinsic gate capacitance and gate-referred thermal-noise voltage Gate-referred flicker-noise voltage and gate-source mismatch voltage Tradeoffs Specific to Current-Mirror Devices Intrinsic bandwidth and drain-referred thermal-noise current Drain-referred flicker-noise current and drain mismatch current Tradeoffs in Figures of Merit Transconductance efficiency and Early voltage Intrinsic voltage gain, bandwidth, and gain-bandwidth Transconductance efficiency and intrinsic bandwidth Thermal-noise efficiency and flicker-noise area efficiency Bandwidth, power, and accuracy with DC offset Bandwidth, power, and accuracy with thermal noise Comparison of bandwidth, power, and accuracy for DC offset and thermal noise Extensions Design of Differential Pairs and Current Minors Using the Analog CMOS Design, Tradeoffs and Optimization Spreadsheet Selecting Inversion Coefficient Selecting Channel Length Selecting Drain Cunent Optimizing for DC, Balanced, and AC Performance DC optimization AC optimization Balanced optimization Optimizations at millipower Operation Optimizations at micropower Operation Summary of micropower Performance considerations Summary Procedure for Device Optimization 372 References 373 PART II Circuit Design Examples Illustrating Optimization for Analog CMOS Design Design of CMOS Operational Transconductance Amplifiers Optimized for DC, Balanced, and AC Performance Introduction Circuit Description Simple OTAs Cascoded OTAs Circuit Analysis and Performance Optimization Transconductance Simple OTAs Cascoded OTAs 384
7 xü CONTENTS Optimization Output Resistance Simple OTAs CascodedOTAs Optimization Voltage Gain Simple OTAs Cascoded OTAs Optimization Frequency Response Simple OTAs CascodedOTAs Optimization Thermal Noise Simple OTAs Cascoded OTAs Optimization Flicker Noise Simple OTAs CascodedOTAs Optimization Offset Voltage due to Local-Area Mismatch Simple OTAs Cascoded OTAs Optimization Systematic Offset Voltage for Simple OTAs Input and Output Capacitances Simple OTAs CascodedOTAs Optimization Slew Rate Simple OTAs Cascoded OTAs Optimization Input and Output Voltage Ranges Simple OTAs CascodedOTAs Optimization Input, 1 db Compression Voltage Simple OTAs CascodedOTAs Optimization Management of Small-Geometry Effects Design Optimization and Resulting Performance for the Simple OTAs Selection of MOSFET Inversion Coefficients and Channel Lengths DC optimization AC optimization Balanced optimization Predicted and Measured Performance Transconductance, Output resistance, and voltage gain Frequency response 439
8 CONTENTS xiii Thermal noise Flicker noise Offset voltage due to local-area mismatch Systematic offset voltage Input and Output capacitances Slewrate Input and Output voltage ranges Input, ldb compression voltage Layout area Tradeoffs in DC accuracy, low-frequency AC accuracy, voltage gain, and transconductance bandwidth Other Optimizations: Ensuring Input Devices Dominate Thermal Noise Design Optimization and Resulting Performance for the Cascoded OTAs Selection of MOSFET Inversion Coefficients and Channel Lengths DC optimization AC optimization B alanced optimization Predicted and Measured Performance Transconductance, Output resistance, and voltage gain Frequency response Thermal noise Flicker noise Offset voltage due to local-area mismatch Input and Output capacitances Slew rate Input and Output voltage ranges Input, 1 db compression voltage Layout area Tradeoffs in DC accuracy, low-frequency AC accuracy, voltage gain, and transconductance bandwidth Comparison of Performance tradeoffs with those of simple OTAs Other Optimizations: Ensuring Input Devices Dominate Flicker Noise and Local-Area Mismatch Other Optimizations: Complementing the Design Prediction Accuracy for Design Guidance and Optimization 474 References 476 Design of Micropower CMOS Preamplifiers Optimized for Low Thermal and Flicker Noise Introduction Using the Lateral Bipolar Transistor for Low-Flicker-Noise Applications Measures of Preamplifier Noise Performance Thermal-Noise Efficiency Factor Flicker-Noise Area Efficiency Factor Reported Micropower, Low-Noise CMOS Preamplifiers MOS Noise versus the Bias Compliance Voltage Transconductance in Saturation Drain-Source Resistance and Transconductance in the Deep Ohmic Region Gate Noise Voltage Thermal noise Flicker noise 493
9 xiv CONTENTS Drain Noise Current Thermal noise Flicker noise Drain Noise Current with Resistive Source Degeneration Bias compliance voltage Thermal noise Flicker noise Extraction of MOS Flicker-Noise Parameters Preamplifier Input Devices Preamplifier Non-Input Devices Comparisons of Ricker Noise Differential Input Preamplifier Description Circuit Analysis, Performance Optimization, and Predicted Performance Voltage gain Frequency response Thermal noise Thermal noise expressed from DC bias conditions Flicker noise Flicker noise expressed from DC bias conditions Summary of Predicted and Measured Performance MOSFET design selections Resulting preamplifier Performance Design Improvements Single-Ended Input Preamplifier Description Circuit Analysis, Performance Optimization, and Predicted Performance Voltage gain Frequency response Thermal noise Thermal noise expressed from DC bias conditions Flicker noise Flicker noise expressed from DC bias conditions Summary of Predicted and Measured Performance MOSFET design selections Resulting preamplifier Performance Design Improvements Prediction Accuracy for Design Guidance and Optimization Summary of Low-Noise Design Methods and Resulting Challenges in Low-Voltage Processes 550 References 552 Extending Optimization Methods to Smaller-Geometry CMOS Processes and Future Technologies Introduction Using the Inversion Coefficient for CMOS Process Independence and for Extension to Smaller-Geometry Processes Universal g m /I D, V EFF, and V DSsal Characteristics Across CMOS Processes 556
10 CONTENTS Other Nearly Universal Performance Characteristics Across CMOS Processes Porting Designs Across CMOS Processes Extending Design Methods to Smaller-Geometry Processes Enhancing Optimization Methods by Including Gate Leakage Current Effects Using an Inversion Coefficient Measure for Non-CMOS Technologies 561 References 562 Appendix: The Analog CMOS Design, Tradeoffs and Optimization Spreadsheet 565 Index 583
FUNDAMENTALS OF MODERN VLSI DEVICES
19-13- FUNDAMENTALS OF MODERN VLSI DEVICES YUAN TAUR TAK H. MING CAMBRIDGE UNIVERSITY PRESS Physical Constants and Unit Conversions List of Symbols Preface page xi xiii xxi 1 INTRODUCTION I 1.1 Evolution
More informationContents. Contents... v. Preface... xiii. Chapter 1 Introduction...1. Chapter 2 Significant Physical Effects In Modern MOSFETs...
Contents Contents... v Preface... xiii Chapter 1 Introduction...1 1.1 Compact MOSFET Modeling for Circuit Simulation...1 1.2 The Trends of Compact MOSFET Modeling...5 1.2.1 Modeling new physical effects...5
More information444 Index. F Fermi potential, 146 FGMOS transistor, 20 23, 57, 83, 84, 98, 205, 208, 213, 215, 216, 241, 242, 251, 280, 311, 318, 332, 354, 407
Index A Accuracy active resistor structures, 46, 323, 328, 329, 341, 344, 360 computational circuits, 171 differential amplifiers, 30, 31 exponential circuits, 285, 291, 292 multifunctional structures,
More informationANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS
ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,
More informationANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS
ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,
More informationFundamentals of Power Semiconductor Devices
В. Jayant Baliga Fundamentals of Power Semiconductor Devices 4y Spri ringer Contents Preface vii Chapter 1 Introduction 1 1.1 Ideal and Typical Power Switching Waveforms 3 1.2 Ideal and Typical Power Device
More informationIndex. Small-Signal Models, 14 saturation current, 3, 5 Transistor Cutoff Frequency, 18 transconductance, 16, 22 transit time, 10
Index A absolute value, 308 additional pole, 271 analog multiplier, 190 B BiCMOS,107 Bode plot, 266 base-emitter voltage, 16, 50 base-emitter voltages, 296 bias current, 111, 124, 133, 137, 166, 185 bipolar
More informationDesign of Analog CMOS Integrated Circuits
Design of Analog CMOS Integrated Circuits Behzad Razavi Professor of Electrical Engineering University of California, Los Angeles H Boston Burr Ridge, IL Dubuque, IA Madison, WI New York San Francisco
More informationCONTENTS. 2.2 Schrodinger's Wave Equation 31. PART I Semiconductor Material Properties. 2.3 Applications of Schrodinger's Wave Equation 34
CONTENTS Preface x Prologue Semiconductors and the Integrated Circuit xvii PART I Semiconductor Material Properties CHAPTER 1 The Crystal Structure of Solids 1 1.0 Preview 1 1.1 Semiconductor Materials
More informationNAME: Last First Signature
UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences EE 130: IC Devices Spring 2003 FINAL EXAMINATION NAME: Last First Signature STUDENT
More informationTechnology-Independent CMOS Op Amp in Minimum Channel Length
Technology-Independent CMOS Op Amp in Minimum Channel Length A Thesis Presented to The Academic Faculty by Susanta Sengupta In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy
More informationDAT175: Topics in Electronic System Design
DAT175: Topics in Electronic System Design Analog Readout Circuitry for Hearing Aid in STM90nm 21 February 2010 Remzi Yagiz Mungan v1.10 1. Introduction In this project, the aim is to design an adjustable
More informationPHYSICS OF SEMICONDUCTOR DEVICES
PHYSICS OF SEMICONDUCTOR DEVICES PHYSICS OF SEMICONDUCTOR DEVICES by J. P. Colinge Department of Electrical and Computer Engineering University of California, Davis C. A. Colinge Department of Electrical
More informationcost and reliability; power considerations were of secondary importance. In recent years. however, this has begun to change and increasingly power is
CHAPTER-1 INTRODUCTION AND SCOPE OF WORK 1.0 MOTIVATION In the past, the major concern of the VLSI designer was area, performance, cost and reliability; power considerations were of secondary importance.
More informationECEN 474/704 Lab 6: Differential Pairs
ECEN 474/704 Lab 6: Differential Pairs Objective Design, simulate and layout various differential pairs used in different types of differential amplifiers such as operational transconductance amplifiers
More information2. Single Stage OpAmps
/74 2. Single Stage OpAmps Francesc Serra Graells francesc.serra.graells@uab.cat Departament de Microelectrònica i Sistemes Electrònics Universitat Autònoma de Barcelona paco.serra@imb-cnm.csic.es Integrated
More informationSemiconductor Devices
Semiconductor Devices Modelling and Technology Source Electrons Gate Holes Drain Insulator Nandita DasGupta Amitava DasGupta SEMICONDUCTOR DEVICES Modelling and Technology NANDITA DASGUPTA Professor Department
More informationSemiconductor Detector Systems
Semiconductor Detector Systems Helmuth Spieler Physics Division, Lawrence Berkeley National Laboratory OXFORD UNIVERSITY PRESS ix CONTENTS 1 Detector systems overview 1 1.1 Sensor 2 1.2 Preamplifier 3
More informationDESIGN OF A NOVEL CURRENT MIRROR BASED DIFFERENTIAL AMPLIFIER DESIGN WITH LATCH NETWORK. Thota Keerthi* 1, Ch. Anil Kumar 2
ISSN 2277-2685 IJESR/October 2014/ Vol-4/Issue-10/682-687 Thota Keerthi et al./ International Journal of Engineering & Science Research DESIGN OF A NOVEL CURRENT MIRROR BASED DIFFERENTIAL AMPLIFIER DESIGN
More informationMOSFET short channel effects
MOSFET short channel effects overview Five different short channel effects can be distinguished: velocity saturation drain induced barrier lowering (DIBL) impact ionization surface scattering hot electrons
More information1 FUNDAMENTAL CONCEPTS What is Noise Coupling 1
Contents 1 FUNDAMENTAL CONCEPTS 1 1.1 What is Noise Coupling 1 1.2 Resistance 3 1.2.1 Resistivity and Resistance 3 1.2.2 Wire Resistance 4 1.2.3 Sheet Resistance 5 1.2.4 Skin Effect 6 1.2.5 Resistance
More informationAnalysis of 1=f Noise in CMOS Preamplifier With CDS Circuit
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 49, NO. 4, AUGUST 2002 1819 Analysis of 1=f Noise in CMOS Preamplifier With CDS Circuit Tae-Hoon Lee, Gyuseong Cho, Hee Joon Kim, Seung Wook Lee, Wanno Lee, and
More informationChapter 4. CMOS Cascode Amplifiers. 4.1 Introduction. 4.2 CMOS Cascode Amplifiers
Chapter 4 CMOS Cascode Amplifiers 4.1 Introduction A single stage CMOS amplifier cannot give desired dc voltage gain, output resistance and transconductance. The voltage gain can be made to attain higher
More informationA New Model for Thermal Channel Noise of Deep-Submicron MOSFETS and its Application in RF-CMOS Design
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 5, MAY 2001 831 A New Model for Thermal Channel Noise of Deep-Submicron MOSFETS and its Application in RF-CMOS Design Gerhard Knoblinger, Member, IEEE,
More informationFull Paper ACEEE Int. J. on Control System and Instrumentation, Vol. 4, No. 2, June 2013
ACEEE Int J on Control System and Instrumentation, Vol 4, No 2, June 2013 Analys and Design of CMOS Source Followers and Super Source Follower Mr D K Shedge 1, Mr D A Itole 2, Mr M P Gajare 3, and Dr P
More informationMETHODOLOGY FOR THE DIGITAL CALIBRATION OF ANALOG CIRCUITS AND SYSTEMS
METHODOLOGY FOR THE DIGITAL CALIBRATION OF ANALOG CIRCUITS AND SYSTEMS METHODOLOGY FOR THE DIGITAL CALIBRATION OF ANALOG CIRCUITS AND SYSTEMS with Case Studies by Marc Pastre Ecole Polytechnique Fédérale
More informationSubthreshold Op Amp Design Based on the Conventional Cascode Stage
Brigham Young University BYU ScholarsArchive All Theses and Dissertations 2013-06-13 Subthreshold Op Amp Design Based on the Conventional Cascode Stage Kurtis Daniel Cahill Brigham Young University - Provo
More informationECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor
More informationDESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS
DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS DESIGN OF MULTI-BIT DELTA-SIGMA A/D CONVERTERS by Yves Geerts Alcatel Microelectronics, Belgium Michiel Steyaert KU Leuven, Belgium and Willy Sansen KU Leuven,
More informationDesign cycle for MEMS
Design cycle for MEMS Design cycle for ICs IC Process Selection nmos CMOS BiCMOS ECL for logic for I/O and driver circuit for critical high speed parts of the system The Real Estate of a Wafer MOS Transistor
More informationSemiconductor Physics and Devices
Metal-Semiconductor and Semiconductor Heterojunctions The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is one of two major types of transistors. The MOSFET is used in digital circuit, because
More informationIMPROVED CURRENT MIRROR OUTPUT PERFORMANCE BY USING GRADED-CHANNEL SOI NMOSFETS
IMPROVED CURRENT MIRROR OUTPUT PERFORMANCE BY USING GRADED-CHANNEL SOI NMOSFETS Marcelo Antonio Pavanello *, João Antonio Martino and Denis Flandre 1 Laboratório de Sistemas Integráveis Escola Politécnica
More informationMicroelectronic Circuits
SECOND EDITION ISHBWHBI \ ' -' Microelectronic Circuits Adel S. Sedra University of Toronto Kenneth С Smith University of Toronto HOLT, RINEHART AND WINSTON HOLT, RINEHART AND WINSTON, INC. New York Chicago
More informationBJT Amplifier. Superposition principle (linear amplifier)
BJT Amplifier Two types analysis DC analysis Applied DC voltage source AC analysis Time varying signal source Superposition principle (linear amplifier) The response of a linear amplifier circuit excited
More informationRF-CMOS Performance Trends
1776 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 48, NO. 8, AUGUST 2001 RF-CMOS Performance Trends Pierre H. Woerlee, Mathijs J. Knitel, Ronald van Langevelde, Member, IEEE, Dirk B. M. Klaassen, Luuk F.
More information1286 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY MOSFET Modeling for RF IC Design
1286 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 7, JULY 2005 MOSFET Modeling for RF IC Design Yuhua Cheng, Senior Member, IEEE, M. Jamal Deen, Fellow, IEEE, and Chih-Hung Chen, Member, IEEE Invited
More informationField-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism;
Chapter 3 Field-Effect Transistors (FETs) 3.1 Introduction Field-Effect Transistor (FET) is one of the two major transistors; FET derives its name from its working mechanism; The concept has been known
More informationECEN 474/704 Lab 7: Operational Transconductance Amplifiers
ECEN 474/704 Lab 7: Operational Transconductance Amplifiers Objective Design, simulate and layout an operational transconductance amplifier. Introduction The operational transconductance amplifier (OTA)
More informationLOW POWER FOLDED CASCODE OTA
LOW POWER FOLDED CASCODE OTA Swati Kundra 1, Priyanka Soni 2 and Anshul Kundra 3 1,2 FET, Mody Institute of Technology & Science, Lakshmangarh, Sikar-322331, INDIA swati.kundra87@gmail.com, priyankamec@gmail.com
More informationActive Technology for Communication Circuits
EECS 242: Active Technology for Communication Circuits UC Berkeley EECS 242 Copyright Prof. Ali M Niknejad Outline Comparison of technology choices for communication circuits Si npn, Si NMOS, SiGe HBT,
More informationTWO AND ONE STAGES OTA
TWO AND ONE STAGES OTA F. Maloberti Department of Electronics Integrated Microsystem Group University of Pavia, 7100 Pavia, Italy franco@ele.unipv.it tel. +39-38-50505; fax. +39-038-505677 474 EE Department
More informationChapter 8. Field Effect Transistor
Chapter 8. Field Effect Transistor Field Effect Transistor: The field effect transistor is a semiconductor device, which depends for its operation on the control of current by an electric field. There
More informationCHAPTER 3 TWO DIMENSIONAL ANALYTICAL MODELING FOR THRESHOLD VOLTAGE
49 CHAPTER 3 TWO DIMENSIONAL ANALYTICAL MODELING FOR THRESHOLD VOLTAGE 3.1 INTRODUCTION A qualitative notion of threshold voltage V th is the gate-source voltage at which an inversion channel forms, which
More information8. Characteristics of Field Effect Transistor (MOSFET)
1 8. Characteristics of Field Effect Transistor (MOSFET) 8.1. Objectives The purpose of this experiment is to measure input and output characteristics of n-channel and p- channel field effect transistors
More informationEducation on CMOS RF Circuit Reliability
Education on CMOS RF Circuit Reliability Jiann S. Yuan 1 Abstract This paper presents a design methodology to study RF circuit performance degradations due to hot carrier and soft breakdown. The experimental
More informationUNIT 3: FIELD EFFECT TRANSISTORS
FIELD EFFECT TRANSISTOR: UNIT 3: FIELD EFFECT TRANSISTORS The field effect transistor is a semiconductor device, which depends for its operation on the control of current by an electric field. There are
More informationDepartment of Electrical Engineering IIT Madras
Department of Electrical Engineering IIT Madras Sample Questions on Semiconductor Devices EE3 applicants who are interested to pursue their research in microelectronics devices area (fabrication and/or
More informationChapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier
Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in double-ended
More informationTransconductance Amplifier Structures With Very Small Transconductances: A Comparative Design Approach
770 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 6, JUNE 2002 Transconductance Amplifier Structures With Very Small Transconductances: A Comparative Design Approach Anand Veeravalli, Student Member,
More informationIn this lecture we will begin a new topic namely the Metal-Oxide-Semiconductor Field Effect Transistor.
Solid State Devices Dr. S. Karmalkar Department of Electronics and Communication Engineering Indian Institute of Technology, Madras Lecture - 38 MOS Field Effect Transistor In this lecture we will begin
More informationGennady Gildenblat. Editor. Compact Modeling. Principles, Techniques and Applications. Springer
Gennady Gildenblat Editor Compact Modeling Principles, Techniques and Applications Springer Contents Part I Compact Models of MOS Transistors 1 Surface-Potential-Based Compact Model of Bulk MOSFET 3 Gennady
More informationDesigning CMOS folded-cascode operational amplifier with flicker noise minimisation
Microelectronics Journal 32 (200) 69 73 Short Communication Designing CMOS folded-cascode operational amplifier with flicker noise minimisation P.K. Chan*, L.S. Ng, L. Siek, K.T. Lau Microelectronics Journal
More information55:041 Electronic Circuits
55:041 Electronic Circuits MOSFETs Sections of Chapter 3 &4 A. Kruger MOSFETs, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width = 1 10-6 m or less Thickness = 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor
More informationLecture-45. MOS Field-Effect-Transistors Threshold voltage
Lecture-45 MOS Field-Effect-Transistors 7.4. Threshold voltage In this section we summarize the calculation of the threshold voltage and discuss the dependence of the threshold voltage on the bias applied
More informationLow-Voltage Wide Linear Range Tunable Operational Transconductance Amplifier
Low-Voltage Wide Linear Range Tunable Operational Transconductance Amplifier A dissertation submitted in partial fulfillment of the requirement for the award of degree of Master of Technology in VLSI Design
More informationA Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions
Brigham Young University BYU ScholarsArchive All Theses and Dissertations 2012-01-28 A Design Basis for Composite Cascode Stages Operating in the Subthreshold/Weak Inversion Regions Taylor Matt Waddel
More informationMSE 410/ECE 340: Electrical Properties of Materials Fall 2016 Micron School of Materials Science and Engineering Boise State University
MSE 410/ECE 340: Electrical Properties of Materials Fall 2016 Micron School of Materials Science and Engineering Boise State University Practice Final Exam 1 Read the questions carefully Label all figures
More informationSWITCHED-CURRENTS an analogue technique for digital technology
SWITCHED-CURRENTS an analogue technique for digital technology Edited by С Toumazou, ]. B. Hughes & N. C. Battersby Supported by the IEEE Circuits and Systems Society Technical Committee on Analog Signal
More informationLecture 4 -- Tuesday, Sept. 19: Non-uniform injection and/or doping. Diffusion. Continuity/conservation. The five basic equations.
6.012 ELECTRONIC DEVICES AND CIRCUITS Schedule -- Fall 1995 (8/31/95 version) Recitation 1 -- Wednesday, Sept. 6: Review of 6.002 models for BJT. Discussion of models and modeling; motivate need to go
More informationLOW SUPPLY VOLTAGE, LOW NOISE FULLY DIFFERENTIAL PROGRAMMABLE GAIN AMPLIFIERS
LOW SUPPLY VOLTAGE, LOW NOISE FULLY DIFFERENTIAL PROGRAMMABLE GAIN AMPLIFIERS A. Pleteršek, D. Strle, J. Trontelj Microelectronic Laboratory University of Ljubljana, Tržaška 25, 61000 Ljubljana, Slovenia
More informationUNIT-1 Bipolar Junction Transistors. Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press
UNIT-1 Bipolar Junction Transistors Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press Figure 6.1 A simplified structure of the npn transistor. Microelectronic Circuits, Sixth
More informationa leap ahead in analog
Analog modeling requirements for HV CMOS technology Ehrenfried Seebacher 2011-12-15 a leap ahead in analog Presentation Overview Design perspective on High Performance Analog HV CMOS Analog modeling requirements
More informationAN increasing number of video and communication applications
1470 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 9, SEPTEMBER 1997 A Low-Power, High-Speed, Current-Feedback Op-Amp with a Novel Class AB High Current Output Stage Jim Bales Abstract A complementary
More informationPROCESS and environment parameter variations in scaled
1078 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 53, NO. 10, OCTOBER 2006 Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits Ranjith Kumar
More informationLecture 190 CMOS Technology, Compatible Devices (10/28/01) Page 190-1
Lecture 190 CMOS Technology, Compatible Devices (10/28/01) Page 190-1 LECTURE 190 CMOS TECHNOLOGY-COMPATIBLE DEVICES (READING: Text-Sec. 2.9) INTRODUCTION Objective The objective of this presentation is
More informationCHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS
CHAPTER 8 DIFFERENTIAL AND MULTISTAGE AMPLIFIERS Chapter Outline 8.1 The CMOS Differential Pair 8. Small-Signal Operations of the MOS Differential Pair 8.3 The BJT Differential Pair 8.4 Other Non-ideal
More informationA Novel Design of Low Voltage,Wilson Current Mirror based Wideband Operational Transconductance Amplifier
A Novel Design of Low Voltage,Wilson Current Mirror based Wideband Operational Transconductance Amplifier Kehul A. Shah 1, N.M.Devashrayee 2 1(Associative Prof., Department of Electronics and Communication,
More informationDrive performance of an asymmetric MOSFET structure: the peak device
MEJ 499 Microelectronics Journal Microelectronics Journal 30 (1999) 229 233 Drive performance of an asymmetric MOSFET structure: the peak device M. Stockinger a, *, A. Wild b, S. Selberherr c a Institute
More informationLOW VOLTAGE / LOW POWER RAIL-TO-RAIL CMOS OPERATIONAL AMPLIFIER FOR PORTABLE ECG
LOW VOLTAGE / LOW POWER RAIL-TO-RAIL CMOS OPERATIONAL AMPLIFIER FOR PORTABLE ECG A DISSERTATION SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL OF THE UNIVERSITY OF MINNESOTA BY BORAM LEE IN PARTIAL FULFILLMENT
More informationWhat is the typical voltage gain of the basic two stage CMOS opamp we studied? (i) 20dB (ii) 40dB (iii) 80dB (iv) 100dB
Department of Electronic ELEC 5808 (ELG 6388) Signal Processing Electronics Final Examination Dec 14th, 2010 5:30PM - 7:30PM R. Mason answer all questions one 8.5 x 11 crib sheets allowed 1. (5 points)
More informationECE 340 Lecture 40 : MOSFET I
ECE 340 Lecture 40 : MOSFET I Class Outline: MOS Capacitance-Voltage Analysis MOSFET - Output Characteristics MOSFET - Transfer Characteristics Things you should know when you leave Key Questions How do
More informationDirect calculation of metal oxide semiconductor field effect transistor high frequency noise parameters
Direct calculation of metal oxide semiconductor field effect transistor high frequency noise parameters C. H. Chen and M. J. Deen a) Engineering Science, Simon Fraser University, Burnaby, British Columbia
More informationRail-To-Rail Output Op-Amp Design with Negative Miller Capacitance Compensation
Rail-To-Rail Op-Amp Design with Negative Miller Capacitance Compensation Muhaned Zaidi, Ian Grout, Abu Khari bin A ain Abstract In this paper, a two-stage op-amp design is considered using both Miller
More informationMultimode 2.4 GHz Front-End with Tunable g m -C Filter. Group 4: Nick Collins Trevor Hunter Joe Parent EECS 522 Winter 2010
Multimode 2.4 GHz Front-End with Tunable g m -C Filter Group 4: Nick Collins Trevor Hunter Joe Parent EECS 522 Winter 2010 Overview Introduction Complete System LNA Mixer Gm-C filter Conclusion Introduction
More informationMicroelectronic Circuits II. Ch 10 : Operational-Amplifier Circuits
Microelectronic Circuits II Ch 0 : Operational-Amplifier Circuits 0. The Two-stage CMOS Op Amp 0.2 The Folded-Cascode CMOS Op Amp CNU EE 0.- Operational-Amplifier Introduction - Analog ICs : operational
More informationSub-Threshold Region Behavior of Long Channel MOSFET
Sub-threshold Region - So far, we have discussed the MOSFET behavior in linear region and saturation region - Sub-threshold region is refer to region where Vt is less than Vt - Sub-threshold region reflects
More informationAn introduction to Depletion-mode MOSFETs By Linden Harrison
An introduction to Depletion-mode MOSFETs By Linden Harrison Since the mid-nineteen seventies the enhancement-mode MOSFET has been the subject of almost continuous global research, development, and refinement
More informationPERFORMANCE CHARACTERISTICS OF EPAD PRECISION MATCHED PAIR MOSFET ARRAY
TM ADVANCED LINEAR DEVICES, INC. e EPAD E N A B L E D PERFORMANCE CHARACTERISTICS OF EPAD PRECISION MATCHED PAIR MOSFET ARRAY GENERAL DESCRIPTION ALDxx/ALD9xx/ALDxx/ALD9xx are high precision monolithic
More informationA High-Gain, Low-Power CMOS Operational Amplifier Using Composite Cascode Stage in the Subthreshold Region
Brigham Young University BYU ScholarsArchive All Theses and Dissertations 2011-03-15 A High-Gain, Low-Power CMOS Operational Amplifier Using Composite Cascode Stage in the Subthreshold Region Rishi Pratap
More informationAnalog IC Design. Lecture 1,2: Introduction & MOS transistors. Henrik Sjöland. Dept. of Electrical and Information Technology
Analog IC Design Lecture 1,2: Introduction & MOS transistors Henrik.Sjoland@eit.lth.se Part 1: Introduction Analogue IC Design (7.5hp, lp2) CMOS Technology Analog building blocks in CMOS Single- and multiple
More informationExam Below are two schematics of current sources implemented with MOSFETs. Which current source has the best compliance voltage?
Exam 2 Name: Score /90 Question 1 Short Takes 1 point each unless noted otherwise. 1. Below are two schematics of current sources implemented with MOSFETs. Which current source has the best compliance
More informationMOS Field-Effect Transistors (MOSFETs)
6 MOS Field-Effect Transistors (MOSFETs) A three-terminal device that uses the voltages of the two terminals to control the current flowing in the third terminal. The basis for amplifier design. The basis
More informationDigital Electronics. By: FARHAD FARADJI, Ph.D. Assistant Professor, Electrical and Computer Engineering, K. N. Toosi University of Technology
K. N. Toosi University of Technology Chapter 7. Field-Effect Transistors By: FARHAD FARADJI, Ph.D. Assistant Professor, Electrical and Computer Engineering, K. N. Toosi University of Technology http://wp.kntu.ac.ir/faradji/digitalelectronics.htm
More informationALow Voltage Wide-Input-Range Bulk-Input CMOS OTA
Analog Integrated Circuits and Signal Processing, 43, 127 136, 2005 c 2005 Springer Science + Business Media, Inc. Manufactured in The Netherlands. ALow Voltage Wide-Input-Range Bulk-Input CMOS OTA IVAN
More informationSession 2 MOS Transistor for RF Circuits
Session 2 MOS Transistor for RF Circuits Session Speaker Chandramohan P. Session Contents MOS transistor basics MOS equivalent circuit Single stage amplifiers Opamp design Session objectives To understand
More informationE3 237 Integrated Circuits for Wireless Communication
E3 237 Integrated Circuits for Wireless Communication Lecture 8: Noise in Components Gaurab Banerjee Department of Electrical Communication Engineering, Indian Institute of Science, Bangalore banerjee@ece.iisc.ernet.in
More informationThe Art of ANALOG LAYOUT Second Edition
The Art of ANALOG LAYOUT Second Edition Alan Hastings 3 EARSON Pearson Education International Contents Preface to the Second Edition xvii Preface to the First Edition xix Acknowledgments xxi 1 Device
More informationLECTURE 09 LARGE SIGNAL MOSFET MODEL
Lecture 9 Large Signal MOSFET Model (5/14/18) Page 9-1 LECTURE 9 LARGE SIGNAL MOSFET MODEL LECTURE ORGANIZATION Outline Introduction to modeling Operation of the MOS transistor Simple large signal model
More informationAdvanced Operational Amplifiers
IsLab Analog Integrated Circuit Design OPA2-47 Advanced Operational Amplifiers כ Kyungpook National University IsLab Analog Integrated Circuit Design OPA2-1 Advanced Current Mirrors and Opamps Two-stage
More informationField Effect Transistors (npn)
Field Effect Transistors (npn) gate drain source FET 3 terminal device channel e - current from source to drain controlled by the electric field generated by the gate base collector emitter BJT 3 terminal
More informationPreface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate
Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation
More informationUnit III FET and its Applications. 2 Marks Questions and Answers
Unit III FET and its Applications 2 Marks Questions and Answers 1. Why do you call FET as field effect transistor? The name field effect is derived from the fact that the current is controlled by an electric
More informationHigh Voltage Operational Amplifiers in SOI Technology
High Voltage Operational Amplifiers in SOI Technology Kishore Penmetsa, Kenneth V. Noren, Herbert L. Hess and Kevin M. Buck Department of Electrical Engineering, University of Idaho Abstract This paper
More informationLINEAR INTEGRATED SYSTEMS, INC.
LINEAR INTEGRATED SYSTEMS, INC. 4042 Clipper Court Fremont, CA 94538-6540 sales@linearsystems.com A Linear Integrated Systems, Inc. White Paper Consider the Discrete JFET When You Have a Priority Performance
More informationAnalog and Telecommunication Electronics
Politecnico di Torino - ICT School Analog and Telecommunication Electronics F2 Active power devices»mos»bjt» IGBT, TRIAC» Safe Operating Area» Thermal analysis 30/05/2012-1 ATLCE - F2-2011 DDC Lesson F2:
More informationAnalysis and Design of Analog Integrated Circuits Lecture 8. Cascode Techniques
Analysis and Design of Analog Integrated Circuits Lecture 8 Cascode Techniques Michael H. Perrott February 15, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. Review of Large Signal Analysis
More informationCDTE and CdZnTe detector arrays have been recently
20 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 44, NO. 1, FEBRUARY 1997 CMOS Low-Noise Switched Charge Sensitive Preamplifier for CdTe and CdZnTe X-Ray Detectors Claudio G. Jakobson and Yael Nemirovsky
More informationMicroelectronics Part 2: Basic analog CMOS circuits
GBM830 Dispositifs Médicaux Intelligents Microelectronics Part : Basic analog CMOS circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim!! http://www.cours.polymtl.ca/gbm830/! mohamad.sawan@polymtl.ca!
More informationAnalysis and Design of Analog Integrated Circuits Lecture 18. Key Opamp Specifications
Analysis and Design of Analog Integrated Circuits Lecture 8 Key Opamp Specifications Michael H. Perrott April 8, 0 Copyright 0 by Michael H. Perrott All rights reserved. Recall: Key Specifications of Opamps
More informationIntroduction to semiconductor technology
Introduction to semiconductor technology Outline 7 Field effect transistors MOS transistor current equation" MOS transistor channel mobility Substrate bias effect 7 Bipolar transistors Introduction Minority
More information