Announcements. Advanced Digital Integrated Circuits. Midterm feedback mailed back Homework #3 posted over the break due April 8

Transcription

1 EE241 - Spring 21 Advanced Digital Integrated Circuits Lecture 18: Dynamic Voltage Scaling Announcements Midterm feedback mailed back Homework #3 posted over the break due April 8 Reading: Chapter 5, 6, 8, 1, from Rabaey LPDE 2 1

2 Outline Last lecture Power-performance tradeoffs through supply voltage This lecture DVS Clock gating 3 Power-Performance Power Performance Tradeoffs through Supply Voltage 2

3 Power /Energy Optimization Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Sleep Mode Run Time Active Logic design Scaled V DD Trans. sizing Clock gating DFS, DVS Multi-V DD Leakage Stack effects Trans sizing Scaling V DD + Multi-V Th Sleep T s Multi-V DD Variable V Th + Input control + Variable V Th 5 Power /Energy Optimization Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Sleep Mode Run Time Active Logic design Scaled V DD Trans. sizing Clock gating DFS, DVS Multi-V DD Leakage Stack effects Trans sizing Scaling V DD + Multi-V Th Sleep T s Multi-V DD Variable V Th + Input control + Variable V Th 6 3

4 Adaptive Supply Voltages 7 Processors for Portable Devices Per rformance (MIP PS) Dynamic Voltage Scaling PDAs Pocket-PCs Notebook Computers Processor Energy (Watt*sec) Eliminate performance energy trade-off ISSCC 8 4

5 Typical MPEG IDCT Histogram 9 Processor Usage Model Desired Throughput Compute-intensive and low-latency processes Maximum Processor Speed Background and System Idle high-latency processes System Optimizations: Maximize Peak Throughput Minimize Average Energy/operation time ISSCC 1 5

6 Common Design Approaches (Fixed VDD) Delive ered Throughput Compute ASAP: Always high throughput Clock Frequency Reduction: f CLK Reduced Excess throughput time Energy/operation remains unchanged while throughput scaled down with f CLK time 11 Scale V DD with Clock Frequency Ene ergy/operation 1.5 ~1x Energy Reduction 1.1V Constant supply voltage 3.3V Reduce V DD, slow circuits down..5 1 Throughput ( f CLK ) ISSCC 12 6

7 CMOS Circuits Track Over V DD 1. LK No ormalized max. f C.5 Inverter RingOsc RegFile SRAM VT 2V T 3V T 4V T V DD Delay tracks within +/- 1% ISSCC 13 Dynamic Voltage Scaling (DVS) 1 Vary f CLK,V DD 2 Dynamically adapt Delivered Throughput time Dynamically scale energy/operation with throughput. ISSCC Always minimize speed minimize average energy/operation. Extend battery life up to 1x with the exact same hardware! 14 7

8 Operating System Sets Processor Speed DVS requires a voltage scheduler (VS). VS predicts workload to estimate CPU cycles. Applications supply completion deadlines. Processor Speed (MPEG) CPU cycles time F DESIRED F DESIRED (M Hz) Time (sec) 15 Converter Loop Sets V DD, f CLK I DD ST RCounter f CLK f 1MHz Latch Ring Oscillator Processor 7 F MEAS Set by OS O.S F DES + F ERR P ENAB N ENAB Register Digital Loop Filter Buck converter Feedback loop sets V DD so that F ERR. Ring oscillator delay-matched to CPU critical paths. Custom loop implementation Can optimize C DD. L V DD C DD ISSCC 16 8

9 Design Over Wide Range of Voltages Circuit design constraints. (Functional verification) Circuit delay variation. (Timing verification) Noise margin reduction. (Power grid, coupling) Delay sensitivity. (Local power distribution) Design verification complexity similar to high-performance processor fixed V DD 17 Delay Variation & Circuit Constraints 1. CLK No ormalized max. f C.5 Inverter RingOsc RegFile SRAM VT 2V T 3V T 4V V T DD Cannot use NMOS pass gates fails for V DD < 2V T. Functional verification only needed at one V DD value. ISSCC 18 9

10 Relative Delay Variation Perc cent Delay Varia ation Delay relative to ring oscillator Four extreme cases of critical paths: All vary monotonically with V DD. -2 V T 2V T 3V V T 4V T DD Timing verification only needed at min. & max. V DD. Gate Interconnect Diffusion Series ISSCC 19 Delay Sensitivity Delay Delay V DD, VDD I( VDD ) R Delay V Delay( V ) DD DD lized Delay / Delay Normal ISSCC V T 2V T 3V V T 4V T DD Design of local power grid (for timing constraints) only need to consider V DD 2V T. 2 1

11 Multiple Path Tracking A. Drake, ISSCC 7 21 Design for Dynamically Varying VDD Static CMOS logic. Ring oscillator. Dynamic logic (& tri-state busses). Sense amp (& memory cell). Max. allowed dv DD /dt Min. C DD = 1nF (.6 m) Circuits continue to properly operate as V DD changes 22 11

12 Static CMOS Logic V DD V in = V out = V DD r ds PMOS C L V out max. = 4ns.6 m CMOS: dv DD /dt < 2V/ s Static CMOS robustly operates with varying V DD. 23 Ring Oscillator 4 Simulated with dv DD /dt = 2V/ s 3 Volts 2 1 V DD f CLK Time (ns) Output f CLK instantaneously adapts to new V DD

13 Dynamic Logic clk V DD V out clk = 1 Errors V in clk Volts V DD V out V DD V DD False logic low: V DD > V TP Latch-up: V DD > V be Time.6 m CMOS: dv DD /dt < 2V/ s Cannot gate clock in evaluation state. Tri-state busses fail similarly Use hold circuit. 25 Measured System Performance & Energy rystone 2.1 MIP PS Dh x Static V DD Dynamic V DD mw/mips (3.8V) 2 6 mw/mips (1.2V) Energy (mw/mips) Dynamic operation can increase energy efficiency > 1x. ISSCC 26 13

14 V DD -Hopping #n #n+1 Time Next milestone n-th slice finished here Application slicing and software feedback guarantee real-time operation. Normalized powe er MPEG-4 encoding 1 Transition.8 time between ƒ.6 levels = 2µs # of frequency levels Two hopping levels are sufficient Power /Energy Optimization Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Sleep Mode Run Time Active Logic design Scaled V DD Trans. sizing Clock gating DFS, DVS Multi-V DD Leakage Stack effects Trans sizing Scaling V DD + Multi-V Th Sleep T s Multi-V DD Variable V Th + Input control + Variable V Th 28 14

15 Clock gating Requires careful skew control... Well handled in today s EDA tools 29 Clock-gating efficiently reduces power Without clock gating With clock gating 8.5mW 3.6mW MPEG4 decoder Power [mw] 9% of F/F s were clock-gated. 7% power reduction by clockgating alone. Courtesy M. Ohashi, Matsushita, ISSCC 22 VDE MIF 896Kb SRAM DEU DSP/ HIF 3 15

16 Local Clock Gating D CKI D I CKIB CKIB Q.5 Data-Transition Look-Ahead Pulse Generator XNOR CP.85.5 CKIB CKI Clock on demand Flip-flop 31 Power /Energy Optimization Space Constant Throughput/Latency Variable Throughput/Latency Energy Design Time Sleep Mode Run Time Active Logic design Scaled V DD Trans. sizing Clock gating DFS, DVS Multi-V DD Leakage Stack effects Trans sizing Scaling V DD + Multi-V Th Sleep T s Multi-V DD Variable V Th + Input control + Variable V Th 32 16

17 Circuit-Level Activity Encoding Conditional Inversion Coding for Interconnect 33 Number Representation 34 17

18 Next Lecture Leakage 35 18