Timing analysis can be done right after synthesis. But it can only be accurately done when layout is available

Transcription

1 Timing Analysis Lecture 9 ECE 156A-B 1 General Timing analysis can be done right after synthesis But it can only be accurately done when layout is available Timing analysis at an early stage is not accurate because no detailed physical information is available ECE 156A-B 2 1

2 Tools Synopsys set of tools Design Compiler for synthesis and optimization Primetime is pretty much an industrial standard tool for timing analysis Cell-based timing analysis Pathmill is a tool to calculate timing at transistor level ECE 156A-B 3 A cell delay model a slew b AND c load The delay of a rising => c rising is modeled as a function of (input slew, output load) The delay of a => c is modeled assuming that b is at its steady value wire delay is modeled differently or assumed to be included in the cell model ECE 156A-B 4 2

3 Typical delay model Cell-based Interconnect is considered by worst-case model Pin-to-pin delay (a => c, b => c) Delay is a function of Input transition Output load Vdd and temperature [min, typ, max] model Also separate rising delay and falling delay ECE 156A-B 5 Cell-based timing analysis Full-chip timing analysis (Primetime) Actual delay values layout extraction (find output loads) Cell delay library (company-dependent) (Pathmill) SPICE models for transistors and wires (examples: BSIM3 spice model) process parameters for transistors and wires (examples: Vt, L, length, thickness, etc.) ECE 156A-B 6 3

4 Type of Timing Paths to check Combinational Logic Register Combinational Logic Register Combinational Logic Clock 1. Input -> register 2. Register -> register 3. Register -> output 4. Input -> output ECE 156A-B 7 Input delay constraint ECE 156A-B 8 4

5 Output delay constraint ECE 156A-B 9 Clock Scheduling LD: logic delay Register i Combinational Logic Register j Clock t i t j clock skew = ti tj ECE 156A-B 10 5

6 Timing constraint actual margin T clock > t clk_to_output + t comb_max + t setup + t skew ECE 156A-B 11 Timing check: setup time The setup time constraint of a flip-flop specifies a time interval before the active edge of clock. Data must arrive before the interval. $setup(data, posedge clk, 5); ECE 156A-B 12 6

7 Setup time example ECE 156A-B 13 Timing check: hold time The hold time constraint specifies an interval after the active edge of clock. Data must be stable in the interval. $hold(data, posedge clk, 2); ECE 156A-B 14 7

8 Hold time example ECE 156A-B 15 Pulse Width The width of the clock pulse must not be too small. $width(posedge clock_a, t_mpw); ECE 156A-B 16 8

9 Clock Skew Signal skew is the arriving time difference of two signals. Clock skew should be low. $skew(negedge clk1, negedge clk2, t_skew); ECE 156A-B 17 Verilog timing check Verilog timing check provides only rough check Usually it needs a separate tool (timing analysis tool) to do the check It is not part of the verilog simulator nor part of the synthesis process ECE 156A-B 18 9

10 Timing Constraint Examples t j hold setup t i skew LD min LD max skew skew ij constraint: hold max (t i t j ) < LD min i.e. (hold skew) < LD skew ij = t i t j < CP LD max setup max i.e. LD < (clock skew) setup LD: Logic Delay ECE 156A-B 19 Factors that affect timing ECE 156A-B 20 10

11 Multiple clock domains clock skew = arrival time of clk_1 arrive time of clk_2 ECE 156A-B 21 Model to check via timing DAG (find worst LDs between FFs) ECE 156A-B 22 11

12 Static Timing Analysis 7/4/-3 5/3/ /6/-3 11 given 4/7/3 4 20/17/ /18/0 23/20/-3 8/8/0 3 11/11/0 Arrival time: input -> output, (take max) Required arrival time: output -> input, (take min) Slack = required arrival time arrival time ECE 156A-B 23 False Paths (don t affect timing) Can t be sensitized! [3:5, 2:3] [3:5, 2:3] [3:5, 2:3] Max path delay = 15? Min, max rising Min, max falling ECE 156A-B 24 12

13 Logical false path ECE 156A-B 25 Dynamically Sensitized Paths c d a 0 b a b c The path is not logically sensitizable but time-wise it can be d ECE 156A-B 26 13

14 A circuit with false path ECE 156A-B 27 Gate and Wire Model C R r: resistance per unit length c: capacitance per unit length L rl cl/2 cl/2 ECE 156A-B 28 14

15 Example of Model L 2 0 L 1 1 C 2 2 rl 2 R 0 rl cl 2 /2+C 2 L 3 3 C 3 cl 1 /2 rl 3 3 (L 1 +L 2 +L 3 )c/2 cl 3 /2+C 3 ECE 156A-B 29 Delay Estimation R 2 R 0 R C 2 C 0 C 1 R 3 3 D 0 = R ( C 0 + C 1 + C 2 + C 3 ) D 1 = D 0 + R 1 ( C 1 + C 2 + C 3 ) D 2 = D 1 + R 2 C 2 D 3 = D 1 + R 3 C 3 C 3 ECE 156A-B 30 15

16 Interconnect Delay Interconnect delay is caused by parasitic capacitance and resistance R C C ECE 156A-B 31 Myth:Interconnect Dominates? Delay (ps) Generation (nm) Gate Interconnect (Al+SiO2) Interconnect (Cu+lowk) Sum (Al+SiO2) Sum (Cu+lowk) ECE 156A-B 32 16

17 Interconnect Size Scaling Wire width scales faster than wire height wires are thinner and taller Wires are placed closer Coupling capacitance start to dominate substrate capacitance ECE 156A-B 33 Other: Crosstalk Noise aggressor victim Crosstalk noise may cause Glitch and logical error Extra propagation delay ECE 156A-B 34 17

18 Elimination of Timing Violation Action Increase clock period Reroute critical path Resize and substitute devices Redesign clock tree Substitute a different algorithm Substitute architecture Pipeline/retiming Change technologies Effect Eliminates the violation, constrained by specifications Reduce interconnect delays Reduce device delays and improve setup and hold margins Reduce clock skew Reduce path delays Reduce path delays Reduce path delays Reduce path and device delays ECE 156A-B 35 18