EE 5327 VLSI Design Laboratory. Lab 7 (1 week) - Power Optimization

Transcription

1 EE 5327 VLSI Design Laboratory Lab 7 (1 week) - Power Optimization PURPOSE: The purpose of this lab is to introduce design optimization for power in addition to area and speed. We will be using Design Analyzer. 1. The power a circuit dissipates falls into two broad categories: Static Power and Dynamic Power 1.a. Static power is the power dissipated by a gate when it is not switching, that is, when it is inactive or static. Static power is dissipated in several ways. The largest percentage of static power results from source-to-drain subthreshold leakage, which is caused by reduced threshold voltages that prevent the gate from completely turning off. Static power is also dissipated when current leaks between the diffusion layers and the substrate. For this reason, static power is often called leakage power. 1.b.Dynamic power is the power dissipated when the circuit is active. A circuit is active anytime the voltage on a net changes due to some stimulus applied to the circuit. Because voltage on an input net can change without necessarily resulting in a logic transition on the output, dynamic power can be dissipated even when an output net doesn t change its logic state. The dynamic power of a circuit is composed of Switching power and Internal power 1.c. Switching Power of a driving cell is the power dissipated by the charging and discharging of the load capacitance at the output of the cell. The total load capacitance at the output of a driving cell is the sum of the net and gate capacitances on the driving output. Because such charging and discharging are the result of the logic transitions at the output of the cell, switching power increases as logic transitions increase. Therefore, the switching power of a cell is a function of both the total load capacitance at the cell output and the rate of logic transitions. Switching power comprises 70 to 90% of the power dissipation of an active CMOS circuit. 1.d.Internal power is any power dissipated within the boundary of a cell. During switching, a circuit dissipates internal power by the charging or discharging of any existing capacitances internal to the cell. The definition of internal power includes power dissipated by a momentary short circuit between the P and N transistors of a gate, called short circuit power. To illustrate the cause of short circuit power, consider the simple gate shown in Figure 1. A rising signal is applied at IN. As the signal transitions from low to high, the N type transistor turns on and the P type transistor turns off. However, for a short time during signal transition, both the P and N type transistors can be on Univ. of Minnesota March 9, of 6

2 simultaneously. During this time, current Isc flows from Vdd to GND, causing the dissipation of short circuit power (Psc). For circuits with fast transition times, short circuit power can be small. Rising Signal at IN Vdd Falling Signal at OUT Voltage IIK Voltage IN OUT Time ISC IIK ISW Cload Time IIK: Leakage current ISC: Short circuit current ISW: Switching current GND Figure 1 However, for circuits with slow transition times, short circuit power can account for 30% of the total power dissipated by the gate. Short circuit power is also affected by the dimensions of the transistors and the load capacitance at the gate s output. In most simple library cells, internal power is due mostly to short circuit power. For this reason, the terms internal power and short circuit power are often considered synonymous. 2. Power Compiler, a Design Compiler option, optimizes your design for power. Power Compiler always works within the Design Compiler shell and is transparent to Design Compiler users. During a Design Compiler optimization session, Power Compiler performs additional steps to optimize the design for dynamic and static power. Using the Power Compiler option, Design Compiler can optimize simultaneously for timing, power and area. In addition to the standard inputs to synthesis (RTL or gate-level netlist, technology library, design constraints, and parasitics), Power Compiler uses two other inputs: switching activity of design elements and power constraints. Power Compiler uses switching activity for optimization. Switching activity can originate from gate-level simulation or RTL simulation, and you can annotate all or a portion of the nets in the design. The design constraints for power specify design goals for maximum dynamic power and maximum leakage power. During your optimization session, if Power Compiler finds power constraints set on your design, gate- level power optimization is triggered. If constraints for timing and area are also set, Power Compiler optimizes simultaneously for these design goals as well. Creating a gate-level power-optimized design requires at least two compiles. The first compile optimizes the design for timing and area, which also creates a gate-level netlist containing the nodes on which to annotate switching activity. The second compile optimizes for timing, power, and area after you set power. Advanced topic: In addition to gate-level optimization of your design, Power Compiler also Univ. of Minnesota March 9, of 6

3 offers you optimization at the register transfer level: RTL clock gating. This is a high-level optimization technique that can save a significant amount of power by gating clocks of certain registers that use multiplexers and feedback loops. (We will not be using this in our lab/ projects.) 3. Overview of Methodology: To optimize the power of your gate- level design, 3.a. Choose an RTL architecture for your design. 3.b.Optimize your design for timing and area. 3.c. Set area constraints. 3.d.Set power constraints. You could set which should be given preference: area or power. 3.e. Perform an incremental compile of your design. 4. Here is an example to show how to do power optimization for a counter. You don t need to include this counter optimization results into your lab report. 4.a. Initial setup: Download counter.v file from the course webpage. Create lab7 directory under labs and change into it. Copy the counter.v file into the new directory. 4.b.Copy the file.synopsys_dc.setup from lab5 (not lab 6), modify the line in that file and save it under lab7: (we use cx4000 library in replace of class.v library) define_design_lib LIB7 -path ~/home/grads/ee5327ta/labs/lab7/lib7 (use your userid) 4.c. Create the lib7 directory: mkdir lib7. 4.d.Open Design Vision. 4.e. Make a script file (ex. counter.script) for the counter.v. 4.f. Analyze and Elaborate the counter.v file into the LIB7 directory; analyze -format verilog -lib LIB7 {counter.v} elaborate counter -lib LIB7 4.g.Set the operating conditions to quick_max (cx4551_lib_max) and the wire load to estimated_max (cx4551_lib_max). (By using the commands in lab3,design_vision> set_wire_load_model -name estimated_max -library cx4551_lib_max) 4.h.Define a clock of 20ns; create_clock -name clk -period 20 clk 4.i. Save the design to preserve your attribute settings as counter_before_compile.ddc. You will use this.ddc file and run various optimization schemes on it. 4.j. Set set power_preserve_rtl_hier_names true. This command establishes a correspondence between the names of elements in the RTL design and the names of elements in the gate-level design. And compile the design with low map effort by typing Univ. of Minnesota March 9, of 6

4 the following in the command window: compile -map_effort medium. 4.k.Find out the area, power (report_power), and timing of this circuit. We haven t yet optimized this circuit for power. You ll get a report approximately with the following values. Combinational area: Noncombinational area: Net Interconnect area: undefined (Wire load has zero net area) Total cell area: Total area: undefined Information: The cells in your design are not characterized for internal power. (PWR-229) Cell Internal Power = mw (0%) Net Switching Power = uw (100%) Total Dynamic Power = uw (100%) Cell Leakage Power = data required time data arrival time slack (MET) Now we have to set the switching activity for clk and rst. Type the following commands: set_switching_activity -period toggle_rate 1 rst set_switching_activity -period 20 -toggle_rate 2 clk 6. Run set_max_area This command is used to set the maximum area constraint to 62 units. This value depends on the type of circuit you have designed. 7. Run set_max_dynamic_power 400 uw. This command is used to set a maximum dynamic power consumption of 400 uw. (Do not use this command if you see an error). 8. Run compile -map_effort high 9. Take area, power and timing reports. You ll get something like the following. Univ. of Minnesota March 9, of 6

5 Combinational area: Noncombinational area: Net Interconnect area: undefined (Wire load has zero net area) Total cell area: Total area: undefined Warning: The library cells used by your design are not characterized for internal power. (PWR-26) Cell Internal Power = mw (0%) Net Switching Power = uw (100%) Total Dynamic Power = uw (100%) Cell Leakage Power = data required time data arrival time slack (MET) You might get a bit different values. But you will see that though the power constraint has not been met, the power consumption has come down. Also, have you noticed that the power consumption is way too high for a simple counter? (My guess is the power has been magnified by 1000 times. And I get the data arrival time super large, why?) This is because our cell library is a free one and it does not support internal power characterization which causes the Design Analyzer to produce non-accurate result. The lesson in this lab that we should learn is that we can set power constraints and/or area constraints to optimize your design to meet your need. ( You can play with delay by using set_max_delay -from [from list] -to [to list] value and recompiles). 11. Now you can perform the power optimization on the mealy state machine (one-hot encoding with reduced states) from lab 5( If you don't get one-hot, then just use gray encoding). This is expected to appear in your report. To start afresh, type: remove_design -all. 12. Set up the clock and rest signal period. set_switching_activity -period toggle_rate 1 rst set_switching_activity -period 20 -toggle_rate 2 clk You should attach the area, power and timing reports. Univ. of Minnesota March 9, of 6

6 13. Comment on the power consumption change due to the clock change. 14. Try different constraint settings and repeat the exercise. You might improve upon those values. When you work on your project, you should try power optimization initially to get an idea of the power consumption of your design, and improve it if needed. Univ. of Minnesota March 9, of 6