AND 5GHz ABSTRACTT. easily detected. the transition. for half duration. cycle highh voltage is send. this. data bit frame. the the. data.
|
|
- Cornelia Bryan
- 6 years ago
- Views:
Transcription
1 COMPARISON OF DIFFERENT DESIGNS OF MANCHES STER ENCODER DESIGNED D WITH CMOS INVERTERS USING 32NM UMC CMOS TECHNOLOGY AT 1GHz, 2.5GHz AND 5GHz M. Tech student, Department of ECE, Gyan Vihar School of Engineering and Technology, SGVU, Jaipur, Rajasthan, India 1 M 1DEEPENDRA SINGH BHATI, 2 GHANSHYAM deependra.bhati8300@gmail.com 2 Assistant Professor, Department of ECE, Gyan Vihar School of Engineering and Technology, SGVU, Jaipur, Rajasthan, India ghanu.4us@gmail.com ABSTRACTT Developments in large scale integration resulted in millions of transistors placed on a single chip for execution of intricate circuitry. Due to this placing of large no of transistors within a small area resulted in more heat dissipation and power consumption. To solve these problems many research were carried on and solutions were proposed such as by decreasing the power supply voltage, switching frequency and capacitance of transistor. Different designs of Manchester Encoder has been designed using CMOS inverters, Transmission Gates, NMOS switches, Pass Transistors & GDI (Gate Diffusion Input) celll that can be operated at higher frequencies. All designs have been designed using 32nm UMC CMOS technology and compared at 1GHz, 2.5GHz & 5GHz clock frequency and experimental results show a correct behaviour up to 5 GHz. 1. INTRODUCTION Today, all data transmission systems, magnetic recording and fiber optic data links use modulation codes for efficient transmission of the signal. The Manchester code is a very efficient code as it is level insensitive, selfclocking and the absence of signal can be easily detected as the coded signal has always at least one transition per bit. Manchester Encoding consumes less power and gives desired output at higher frequencies. Manchester coding technique is a digital coding technique in which all the bits of the binary data are arranged in a particular sequence. Heree a bit 1 is represented by transmitting a high voltage for half duration of the input signal and for the next halftime period an inverted signal will be send. When Transmitting 0 in Manchester format, for the first half cycle a low voltage will send, and for the next half cycle a highh voltage is send. Manchester encoding schemee always show the transition in the data signal at the mid point of the data bit frame. Repetition of logic 1 or 0 in NRZ data produces low to highh transition or high to low transitionn respectively at the edge of the data bit frame in Manchester encoded data. Manchester encoded data does not show any change at the edge of the data bit frame if there is change in binary data. Manchester encoder also acts as an XNOR gate. Figure1.1: Waveforms of NRZ Data & Manchester Data 1.11 Advantages of Manchester Encoding In this scheme a single connection can give clock and data information simultaneously. It does not require a separate clock, Digital phase locked loop is used to extract the clock at the receiving data terminal equipment. It does not produce long strings of logic 1 or logic 0 levels. There is a provision of AC coupling of encoded signal as this scheme does not require transmission of DC component. Logic 0 followed by a logic 0 represents the absence of the signal and Logic 1 followed by a logic 1 represents the conflict in signal. The signal power is independent from the data pattern. Reset signal is not required in this scheme. It is very efficient method for use on single core systems such as optical fiber, coaxial cable, Ethernett and Local area networks (LANs). It also acts as an edge triggered D flip flop. 1.2 Disadvantage of Manchester Encoding INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY
2 This encoding scheme is disadvantageous only because its null bandwidth is twice that of the polar NRZ, Unipolar NRZ. In this paper we will discuss two sections, first we will discuss about the previous work (Literature Review) in section 2, and then we will discuss the proposed work under section 3 in which we will use different designs of Manchester encoder. 2. LITERATURE REVIEW The previous work done A 90nm Manchester Code Generator with CMOS switches running at 2.4Ghz and 5Ghz of IEEE. It was the Manchester code generator which was designed at transistor level and it consisted of NMOS switches. The circuit has the same complexity as standard D flip flop and has 26 transistor and 6 NMOS switches. Figure 2.1 shows Manchester encoder circuit. 3.2 Manchester Encoder Design I Figure3.1: Manchester Encoder Design I This Manchester Encoder design has been constructed by using CMOS inverters and NMOS digital switches. It consists of 26 transistors. In this circuit an inverting latch (I 8, I 9 ) is following a non inverting latch (I 3, I 4, I 5 ). When phase f 1 occurs, input signal is passed through inverter I 4. When phase f 2 occurs, inverters I 4 and I 5 latch the input signal and pass it to output node (Out) via inverters I 6 and I 10, at this stage inverter I 9 produces the inverse value of Out. When the next f 1 phase occurs, inverters I 8 and I 9 latch the previously inverted output and pass it to the inverters I 6 and I 10 and then to output node. Therefore we can conclude that rising edge of the clock signal, produces the same input and falling edge of the clock signal produces the inverted input at the output node. Figure2.1 Encoder Block Diagram 3. PROPOSED WORK In this section we will use different circuit to design Manchester Encoder and then check there waveforms, delays and average powers at 32nm at frequency 1 GHz, 2.5 GHz & 5 GHz, but before that we will discuss my work in literature review. 3.1 Literature Review (Proposed Work) I have proposed the previously proposed work on A 90nm Manchester Code Generator with CMOS switches running at 2.4Ghz and 5Ghz. The circuit was designed in 90nm UMC CMOS technology to evaluate the efficiency and experimental results showed correct behaviour up to 5GHz. This encoder was run at V dd =1.2 volt and simulated at typical, fast and slow transistor s corners with clock frequency of 2.4 & 5 GHz. The new simulation was checked on HSPICE simulation tool and found that the work could have been better and better results could be achieved. The average power consumption is more than thousand micro watts i.e. 1168uw at 2.4GHz & 1522uw at 5GHz frequency. The propagation time of both the frequency was improved to 41ps & 56ps from 61ps & 128ps of 2.4 GHz and 5 GHz respectively. 3.3 Manchester Encoder Design II Manchester Encoder is constructed with CMOS inverters and Transmission Gates. In this design when the clock signal is low (logic 0 ), TG (T1) becomes on, T2 & inverter S goes in off condition therefore we get inverted data through inverter I2; when the clock signal is high transmission gate T1 gets off, T2 & S goes in on condition therefore same data is obtained at the output node. At this stage when clock signal is high switch S restricts the fading of the signal through that path where it is connected by making value logic 0. Therefore we can conclude that on the rising edge of the clock signal, the same input gets transmitted to the output, while on the falling edge of the clock signal, we get the inverted input at the output node. INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY
3 Figure3..2: Manchester Encoder Design II 3.4 Manchester Encoder Design III Figure3.4: Manchester Encoder Design IV It consists of two GDI D Latches called Master Slave connection. Each latch is composed of four basic GDI cells and each cell contains 2 transistors therefore it is a eight transistor structure. The parts of the circuit can be divided into two main categories: (a) Body gates These are responsible for the two different statess of the circuit. When clk signal is low, signals pass through PMOS transistors; it is called transparent state of the latch. When clk signal is high, signals pass through NMOS transistors and internal values are stored, it is called holding state of the latch. Figure3.3: Manchester Encoder Design III This circuit is constructed with GDI cells. In this circuit inverter I3 is a GDI cell acting as a multiplexer. Two pass transistors T1 & T2 are operating as digital switches. When clock signal is low, T1 switches ON and T2 switches OFF, due to this data signal gets inverted by inverter I2 and passes through source terminal of PMOS of inverter I3. At this stage when clock signal is low PMOS of inverter I3 switches ON and NMOS switches OFF. Therefore we get the inverted data at the output node. When clock signal is high pass transistor T1 switches OFF and T2 switches ON, data signal passes directly through the source terminal of NMOS of inverter I3. At this stage PMOS of inverter I3 switches OFF and NMOS switches ON. Therefore we get the original data at the output node. (b) Inverters (marked by ) This device maintains the complementary values of the internal signals and device outputs. It also acts as a buffer for the internal signals to restore voltage swing and to improve driving abilities of the outputs. This classification helps in understanding device operation and working. It is noticed that transmission of the signal in body gates is done through the diffusion nodes of the GDI cells. It may result in swing drop of V TH in the output signals. Internal inverters are used as buffer to solve this problem. Size of each transistor in the circuit is adjusted to optimize the circuit performance and to minimize the power delay product. It is the efficient design of Manchester Encoder which contains 18 transistors (16 are shown in diagram and 2 are used to complement the value of D) used to obtain low area and high performance circuits. 3.6 Manchester Encoder Design V 3.5 Manchester Encoder Design IV INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY
4 Figure3.5: Manchester Encoder Design V When clock(clk) signal is low, pass transistors T1 and T4 switches ON and transistors T2 and T3 gets OFF. At this stage slave section acts as a loop containing two inverters and one pass transistor I3, I4 and T4 respectively. This loop stores the previous triggered value of Din. At the same time master section takes new value of Din but does not pass it to the slave section because T3 is OFF. When clock signal is high, pass transistors T2 and T3 becomes ON and new stored value in master section gets passed to the slave section and to the output through the loop of two inverters and one pass transistor I1, I2 and T2 respectively. Both master and slave sections are connected to ground whenever we want to reset the circuit. Figure 4.2: Output at 90nm of f=5 GHz 4.2 Waveform for Design I V (1): Data Signal, V (4): Clock signal, V (16): Output 4. SIMULATION RESULTS In this section waveform of all proposed work has been shown 4.1 Literature Review V (4): Clock signal, V (1): Data signal, V (16): Output Figure 4.3: Output at 32nm for f = 1GHz (Design I) Figure4.1: Output at 90nm for f=2.4 GHz Figure 4.4: Output at 32nm for f = 2.5GHz (Design I) INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY
5 Figure 4.5: Output at 32nm for f = 5GHz (Design I) 4.3 Waveform for Design II V (1): Clock signal, V (3): Data signal, V (7): Output Figure 4.8: Output at 32nm for f = 5GHz (Design II) 4.4 Waveform for Design III V (2): Clock signal, V (1): Data signal, V (9): Output Figure 4.6: Output at 32nm for f = 1GHz (Design II) Figure 4.9: Output at 32nm for f = 1GHz (Design III) Figure 4.7: Output at 32nm for f = 2.5GHz (Design II) Figure 4.10: Output at 32nm for f = 2.5GHz (Design III) INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY
6 Figure 4.11: Output at 32nm for f = 5GHz (Design III) 4.5 Waveform for Design IV V (1): Clock signal, V (4): Data signal, V (12): Output Figure 4.14: Output at 32nm for f = 5GHz (Design IV) 4.6 Waveform for Design V V (1): Clock signal, V (2): Data signal, V (13): Output Figure 4.12: Output at 32nm for f = 1GHz (Design IV) Figure 4.15: Output at 32nm for f = 1GHz (Design V) Figure 4.13: Output at 32nm for f = 2.5GHz (Design IV) Figure 4.16: Output at 32nm for f = 2.5GHz (Design V) INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY
7 Table 5.3: Comparison between different designs Clock Frequency(2.5GHz)& L=32nm Des ign No. No. of Transistor s used Propagation (ps) Average Power (µw) PDP (fj) Figure 4.17: Output at 32nm for f = 5GHz (Design V) 5. RESULT AND COMPARISON Table 5.4: Comparison between different designs Clock Frequency(5GHz)& L=32nm Here Comparison table from Literature review and proposed work is shown. Table 5.2, 5.3 & 5.4 demonstrates the comparison between different designs at 32nm working at 1GHz, 2.5GHz & 5GHz. Desi gn No. No. Of Transisto rs used Propagat ion Average Power PDP (fj) Table 5.1: Comparison from Literature Review (ps) (µw) Clock Frequency (GHz) Previous Work Proposed work Propagation 5 Propagation 61ps 128ps 41ps 56ps Table 5.2: Comparison between different designs Clock Frequency(1GHz)& L=32nm De sig n No. No. of Transisto rs used Propagat ion (ps) Average Power (µw) PDP (fj) CONCLUSION AND FUTURE SCOPE In this thesis, I have designed different forms of Manchester Encoder using CMOS inverters, NMOS digital switches, pass transistors and GDI cell. Each circuit structure has been designed using 32nm UMC CMOS technology. All the designs have been simulated in HSPICE and correct results have been obtained at different clock frequencies (1GHz, 2.5GHz and 5GHz) with supply voltage V dd = 1V and 25 degree centigrade. Design II is considered to be the best optimized design of Manchester Encoder at 5GHz with average power = µW and power delay product (PDP) = 8.966fJ. Thus for high speed communication systems this best optimized design can be used. In future Manchester encoder can be designed at above 5GHz. As technology is getting advanced, 22nm & 16nm UMC CMOS libraries are also available, therefore this encoder can be designed in different forms by using different components to reduce the chip size, average power consumed and total cost of the system by optimizing transistors sizes. INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY
8 REFERENCES 1. P. Benabes, A. Gauthier, J. Oksman, A Manchester code generator running at 1GHz, ICECS, July A. Karagounis, A. Polyzos, B. Kotsos, N. Assimakis, A 90nm Manchester Code Generator with CMOS switches running at 2.4GHz and 5GHz, Systems, Signals and Image Processing, 16th International Conference, June 2009, pp Yu Cherng Hung, Min Ming Kuo, Chiou Kou Tung, and Shao HuiShieh, High Speed CMOS Chip Design for Manchester and Miller Encoder, 2009 Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IEEE ArkadiyMorgenshtein, Alexander Fish and Israel A. Wagner, Gate Diffusion Input (Gdi) A Technique For Low Power Design Of Digital Circuits: Analysis And Characterization, IEEE ArkadiyMorgenshtein, Alexander Fish and Israel A. Wagner, An Efficient Implementation of D Flip Flop Using the GDI Technique, IEEE Gogireddy Sravanthi and Avireni Srinivasulu, Member, IEEE, Performance Analysis of two Manchester Encoders based on TLG s, Modified Current Sink Inverter Multiplexer and Active N MOS Load Inverter Multiplexer, Shi Jingzhuo, Xu Yingxi, Shi Jing Henan University of Science & technology Luoyang, P. R. China Manchester Encoder and Decoder Based on CPLD IEEE BIOGRAPHIES Deependra Singh Bhati is a M.Tech student (V.L.S.I) at Gyan Vihar School of Engineering and Technology, Jaipur, Rajasthan. He has completed his B.Tech (Electronics and Communication) in 2013 under dual Degree Program at Gyan Vihar School of Engineering and Technology, Jaipur. His main research interests are in reducing the size of transistors by reducing W/L ratio & operate them on high frequency. Ghanshyam is an Assistant Professor at Gyan Vihar School of Engineering and Technology. He has completed his M.Tech (V.L.S.I) from Malviya National Institute of Technology in 2013 He has completed his B.Tech in Electronics and Communication from Rajasthan University in INTERNATIONAL JOURNAL OF SCIENCE, ENGINEERING AND TECHNOLOGY
Comparative analysis of different designs of Manchester Encoder based on 45nm UMC CMOS Technology
Comparative analysis of different designs of Manchester Encoder based on 45nm UMC CMOS Technology Sandeep Dasondhi 1, Deepak Vyas 2, Sunil Sharma 3 1 P. G. Scholar, Electronics & Comm., Pacific University,
More informationIMPLEMANTATION OF D FLIP FLOP BASED ON DIFFERENT XOR /XNOR GATE DESIGNS
IMPLEMANTATION OF D FLIP FLOP BASED ON DIFFERENT XOR /XNOR GATE DESIGNS 1 MADHUR KULSHRESTHA, 2 VIPIN KUMAR GUPTA 1 M. Tech. Scholar, Department of Electronics & Communication Engineering, Suresh Gyan
More informationA Low-Power High-speed Pipelined Accumulator Design Using CMOS Logic for DSP Applications
International Journal of Research Studies in Computer Science and Engineering (IJRSCSE) Volume. 1, Issue 5, September 2014, PP 30-42 ISSN 2349-4840 (Print) & ISSN 2349-4859 (Online) www.arcjournals.org
More informationDesign of Low Power Flip Flop Based on Modified GDI Primitive Cells and Its Implementation in Sequential Circuits
Design of Low Power Flip Flop Based on Modified GDI Primitive Cells and Its Implementation in Sequential Circuits Dr. Saravanan Savadipalayam Venkatachalam Principal and Professor, Department of Mechanical
More informationPower And Area Optimization of Pulse Latch Shift Register
International Journal of Engineering Research and Development e-issn: 2278-067X, p-issn: 2278-800X, www.ijerd.com Volume 12, Issue 6 (June 2016), PP.41-45 Power And Area Optimization of Pulse Latch Shift
More informationKeywords: VLSI; CMOS; Pass Transistor Logic (PTL); Gate Diffusion Input (GDI); Parellel In Parellel Out (PIPO); RAM. I.
Comparison and analysis of sequential circuits using different logic styles Shofia Ram 1, Rooha Razmid Ahamed 2 1 M. Tech. Student, Dept of ECE, Rajagiri School of Engg and Technology, Cochin, Kerala 2
More informationA Low Power Array Multiplier Design using Modified Gate Diffusion Input (GDI)
A Low Power Array Multiplier Design using Modified Gate Diffusion Input (GDI) Mahendra Kumar Lariya 1, D. K. Mishra 2 1 M.Tech, Electronics and instrumentation Engineering, Shri G. S. Institute of Technology
More informationGdi Technique Based Carry Look Ahead Adder Design
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 4, Issue 6, Ver. I (Nov - Dec. 2014), PP 01-09 e-issn: 2319 4200, p-issn No. : 2319 4197 Gdi Technique Based Carry Look Ahead Adder Design
More informationLow Power Design Bi Directional Shift Register By using GDI Technique
Low Power Design Bi Directional Shift Register By using GDI Technique C.Ravindra Murthy E-mail: ravins.ch@gmail.com C.P.Rajasekhar Rao E-mail: pcrajasekhar@gmail.com G. Sree Reddy E-mail: srereddy.g@gmail.com
More informationA 10 Bit Low Power Current Steering Digital to Analog Converter Using 45 nm CMOS and GDI Logic
ISSN 2278 0211 (Online) A 10 Bit Low Power Current Steering Digital to Analog Converter Using 45 nm CMOS and GDI Logic Mehul P. Patel M. E. Student (Electronics & communication Engineering) C.U.Shah College
More informationISSN:
343 Comparison of different design techniques of XOR & AND gate using EDA simulation tool RAZIA SULTANA 1, * JAGANNATH SAMANTA 1 M.TECH-STUDENT, ECE, Haldia Institute of Technology, Haldia, INDIA ECE,
More informationCPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4
CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 1 2 3 4 5 6 7 8 9 10 Sum 30 10 25 10 30 40 10 15 15 15 200 1. (30 points) Misc, Short questions (a) (2 points) Postponing the introduction of signals
More informationImplementation of Efficient 5:3 & 7:3 Compressors for High Speed and Low-Power Operations
Volume-7, Issue-3, May-June 2017 International Journal of Engineering and Management Research Page Number: 42-47 Implementation of Efficient 5:3 & 7:3 Compressors for High Speed and Low-Power Operations
More informationDesign And Implementation of FM0/Manchester coding for DSRC. Applications
Design And Implementation of / coding for DSRC Applications Supriya Shivaji Garade, Prof.P.R.Badadapure Department of Electronics and Telecommunication JSPM s Imperial College of Engineering and Research
More informationIC Layout Design of 4-bit Universal Shift Register using Electric VLSI Design System
IC Layout Design of 4-bit Universal Shift Register using Electric VLSI Design System 1 Raj Kumar Mistri, 2 Rahul Ranjan, 1,2 Assistant Professor, RTC Institute of Technology, Anandi, Ranchi, Jharkhand,
More informationModule -18 Flip flops
1 Module -18 Flip flops 1. Introduction 2. Comparison of latches and flip flops. 3. Clock the trigger signal 4. Flip flops 4.1. Level triggered flip flops SR, D and JK flip flops 4.2. Edge triggered flip
More informationImplementation of Low Power High Speed Full Adder Using GDI Mux
Implementation of Low Power High Speed Full Adder Using GDI Mux Thanuja Kummuru M.Tech Student Department of ECE Audisankara College of Engineering and Technology. Abstract The binary adder is the critical
More informationCHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS
70 CHAPTER 5 DESIGN AND ANALYSIS OF COMPLEMENTARY PASS- TRANSISTOR WITH ASYNCHRONOUS ADIABATIC LOGIC CIRCUITS A novel approach of full adder and multipliers circuits using Complementary Pass Transistor
More informationA High Performance Asynchronous Counter using Area and Power Efficient GDI T-Flip Flop
Indian Journal of Science and Technology, Vol 8(7), 622 628, April 2015 ISSN (Print) : 0974-6846 ISSN (Online) : 0974-5645 DOI: 10.17485/ijst/2015/v8i7/62847 A High Performance Asynchronous Counter using
More informationDesign of New Full Swing Low-Power and High- Performance Full Adder for Low-Voltage Designs
International Academic Institute for Science and Technology International Academic Journal of Science and Engineering Vol. 2, No., 201, pp. 29-. ISSN 2-9 International Academic Journal of Science and Engineering
More informationComparator Design Analysis using Efficient Low Power Full Adder Meena Aggarwal 1, Rajesh Mehra 2 1 ME student (ECE), 2 Associate Professor
International Journal of Engineering Trends and Technology (IJETT) olume 26 Number 1- August 2015 Comparator Design Analysis using Efficient Low Power Full Adder Meena Aggarwal 1, Rajesh Mehra 2 1 ME student
More informationReduced Area & Improved Delay Module Design of 16- Bit Hamming Codec using HSPICE 22nm Technology based on GDI Technique
International Journal of Scientific and Research Publications, Volume 4, Issue 7, July 2014 1 Reduced Area & Improved Delay Module Design of 16- Bit Hamming Codec using HSPICE 22nm Technology based on
More informationA Literature Survey on Low PDP Adder Circuits
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology IJCSMC, Vol. 4, Issue. 12, December 2015,
More informationA Comparative Analysis of Low Power and Area Efficient Digital Circuit Design
A Comparative Analysis of Low Power and Area Efficient Digital Circuit Design 1 B. Dilli Kumar, 2 A. Chandra Babu, 2 V. Prasad 1 Assistant Professor, Dept. of ECE, Yoganada Institute of Technology & Science,
More informationChapter 6 Combinational CMOS Circuit and Logic Design. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 6 Combinational CMOS Circuit and Logic Design Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Advanced Reliable Systems (ARES) Lab. Jin-Fu Li,
More informationDesign of low-power, high performance flip-flops
Int. Journal of Applied Sciences and Engineering Research, Vol. 3, Issue 4, 2014 www.ijaser.com 2014 by the authors Licensee IJASER- Under Creative Commons License 3.0 editorial@ijaser.com Research article
More informationDESIGN OF EXTENDED 4-BIT FULL ADDER CIRCUIT USING HYBRID-CMOS LOGIC
DESIGN OF EXTENDED 4-BIT FULL ADDER CIRCUIT USING HYBRID-CMOS LOGIC 1 S.Varalakshmi, 2 M. Rajmohan, M.Tech, 3 P. Pandiaraj, M.Tech 1 M.Tech Department of ECE, 2, 3 Asst.Professor, Department of ECE, 1,
More information[Singh*, 5(3): March, 2016] ISSN: (I2OR), Publication Impact Factor: 3.785
IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY COMPARISON OF GDI BASED D FLIP FLOP CIRCUITS USING 90NM AND 180NM TECHNOLOGY Gurwinder Singh*, Ramanjeet Singh ECE Department,
More informationA Low Power and Area Efficient Full Adder Design Using GDI Multiplexer
A Low Power and Area Efficient Full Adder Design Using GDI Multiplexer G.Bramhini M.Tech (VLSI), Vidya Jyothi Institute of Technology. G.Ravi Kumar, M.Tech Assistant Professor, Vidya Jyothi Institute of
More informationInternational Journal of Scientific & Engineering Research, Volume 4, Issue 5, MAY-2013 ISSN
High-Speed 64-Bit Binary using Three Different Logic Styles Anjuli (Student Member IEEE), Satyajit Anand Abstract--High-speed 64-bit binary comparator using three different logic styles is proposed in
More informationEnhancement of Design Quality for an 8-bit ALU
ABHIYANTRIKI An International Journal of Engineering & Technology (A Peer Reviewed & Indexed Journal) Vol. 3, No. 5 (May, 2016) http://www.aijet.in/ eissn: 2394-627X Enhancement of Design Quality for an
More informationElectronic Circuits EE359A
Electronic Circuits EE359A Bruce McNair B206 bmcnair@stevens.edu 201-216-5549 1 Memory and Advanced Digital Circuits - 2 Chapter 11 2 Figure 11.1 (a) Basic latch. (b) The latch with the feedback loop opened.
More informationInvestigation on Performance of high speed CMOS Full adder Circuits
ISSN (O): 2349-7084 International Journal of Computer Engineering In Research Trends Available online at: www.ijcert.org Investigation on Performance of high speed CMOS Full adder Circuits 1 KATTUPALLI
More informationHigh Performance Low-Power Signed Multiplier
High Performance Low-Power Signed Multiplier Amir R. Attarha Mehrdad Nourani VLSI Circuits & Systems Laboratory Department of Electrical and Computer Engineering University of Tehran, IRAN Email: attarha@khorshid.ece.ut.ac.ir
More informationDesign and Implementation of Complex Multiplier Using Compressors
Design and Implementation of Complex Multiplier Using Compressors Abstract: In this paper, a low-power high speed Complex Multiplier using compressor circuit is proposed for fast digital arithmetic integrated
More informationDesign of GDI Based Power Efficient Combinational Circuits and Comparison with Other Logic Styles
Design of GDI Based Power Efficient Combinational Circuits and Comparison with Other Logic Styles Silpa T S, Athira V R Abstract In the modern era, power dissipation has become a major and vital constraint
More informationDESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS
DESIGN OF MULTIPLYING DELAY LOCKED LOOP FOR DIFFERENT MULTIPLYING FACTORS Aman Chaudhary, Md. Imtiyaz Chowdhary, Rajib Kar Department of Electronics and Communication Engg. National Institute of Technology,
More informationAnalysis of Different CMOS Full Adder Circuits Based on Various Parameters for Low Voltage VLSI Design
International Journal of Engineering and Technical Research (IJETR) Analysis of Different CMOS Full Adder Circuits Based on Various Parameters for Low Voltage VLSI Design Mr. Kapil Mangla, Mr. Shashank
More informationCHAPTER 3 NEW SLEEPY- PASS GATE
56 CHAPTER 3 NEW SLEEPY- PASS GATE 3.1 INTRODUCTION A circuit level design technique is presented in this chapter to reduce the overall leakage power in conventional CMOS cells. The new leakage po leepy-
More informationPERFORMANCE ANALYSIS OF LOW POWER FULL ADDER CELLS USING 45NM CMOS TECHNOLOGY
International Journal of Microelectronics Engineering (IJME), Vol. 1, No.1, 215 PERFORMANCE ANALYSIS OF LOW POWER FULL ADDER CELLS USING 45NM CMOS TECHNOLOGY K.Dhanunjaya 1, Dr.MN.Giri Prasad 2, Dr.K.Padmaraju
More informationA Novel Latch design for Low Power Applications
A Novel Latch design for Low Power Applications Abhilasha Deptt. of Electronics and Communication Engg., FET-MITS Lakshmangarh, Rajasthan (India) K. G. Sharma Suresh Gyan Vihar University, Jagatpura, Jaipur,
More informationComparison of High Speed & Low Power Techniques GDI & McCMOS in Full Adder Design
International Conference on Multidisciplinary Research & Practice P a g e 625 Comparison of High Speed & Low Power Techniques & in Full Adder Design Shikha Sharma 1, ECE, Geetanjali Institute of Technical
More information! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential
More informationA DUAL-EDGED TRIGGERED EXPLICIT-PULSED LEVEL CONVERTING FLIP-FLOP WITH A WIDE OPERATION RANGE
A DUAL-EDGED TRIGGERED EXPLICIT-PULSED LEVEL CONVERTING FLIP-FLOP WITH A WIDE OPERATION RANGE Mei-Wei Chen 1, Ming-Hung Chang 1, Pei-Chen Wu 1, Yi-Ping Kuo 1, Chun-Lin Yang 1, Yuan-Hua Chu 2, and Wei Hwang
More informationPower Efficient Arithmetic Logic Unit
Power Efficient Arithmetic Logic Unit Silpa T S, Athira V R Abstract In the modern era, power dissipation has become a major and vital constraint in electronic industry. Many techniques were already introduced
More informationLow Power 32-bit Improved Carry Select Adder based on MTCMOS Technique
Low Power 32-bit Improved Carry Select Adder based on MTCMOS Technique Ch. Mohammad Arif 1, J. Syamuel John 2 M. Tech student, Department of Electronics Engineering, VR Siddhartha Engineering College,
More informationNear-threshold Computing of Single-rail MOS Current Mode Logic Circuits
Research Journal of Applied Sciences, Engineering and Technology 5(10): 2991-2996, 2013 ISSN: 2040-7459; e-issn: 2040-7467 Maxwell Scientific Organization, 2013 Submitted: September 16, 2012 Accepted:
More information2-Bit Magnitude Comparator Design Using Different Logic Styles
International Journal of Engineering Science Invention ISSN (Online): 2319 6734, ISSN (Print): 2319 6726 Volume 2 Issue 1 ǁ January. 2013 ǁ PP.13-24 2-Bit Magnitude Comparator Design Using Different Logic
More informationDigital Transmission
Digital Transmission Line Coding Some Characteristics Line Coding Schemes Some Other Schemes Line coding Signal level versus data level DC component Pulse Rate versus Bit Rate Bit Rate = Pulse Rate x Log2
More informationEE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector
EE584 Introduction to VLSI Design Final Project Document Group 9 Ring Oscillator with Frequency selector Group Members Uttam Kumar Boda Rajesh Tenukuntla Mohammad M Iftakhar Srikanth Yanamanagandla 1 Table
More informationDesign Analysis of 1-bit Comparator using 45nm Technology
Design Analysis of 1-bit Comparator using 45nm Technology Pardeep Sharma 1, Rajesh Mehra 2 1,2 Department of Electronics and Communication Engineering, National Institute for Technical Teachers Training
More informationUNIT-II LOW POWER VLSI DESIGN APPROACHES
UNIT-II LOW POWER VLSI DESIGN APPROACHES Low power Design through Voltage Scaling: The switching power dissipation in CMOS digital integrated circuits is a strong function of the power supply voltage.
More informationPOWER EFFICIENT CARRY PROPAGATE ADDER
POWER EFFICIENT CARRY PROPAGATE ADDER Laxmi Kumre 1, Ajay Somkuwar 2 and Ganga Agnihotri 3 1,2 Department of Electronics Engineering, MANIT, Bhopal, INDIA laxmikumre99@rediffmail.com asomkuwar@gmail.com
More informationII. Previous Work. III. New 8T Adder Design
ISSN: 2277 128X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: High Performance Circuit Level Design For Multiplier Arun Kumar
More informationA Low-Power 12 Transistor Full Adder Design using 3 Transistor XOR Gates
A Low-Power 12 Transistor Full Adder Design using 3 Transistor XOR Gates Anil Kumar 1 Kuldeep Singh 2 Student Assistant Professor Department of Electronics and Communication Engineering Guru Jambheshwar
More informationIntegration of Optimized GDI Logic based NOR Gate and Half Adder into PASTA for Low Power & Low Area Applications
Integration of Optimized GDI Logic based NOR Gate and Half Adder into PASTA for Low Power & Low Area Applications M. Sivakumar Research Scholar, ECE Department, SCSVMV University, Kanchipuram, India. Dr.
More informationLow Power Adiabatic Logic Design
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735.Volume 12, Issue 1, Ver. III (Jan.-Feb. 2017), PP 28-34 www.iosrjournals.org Low Power Adiabatic
More informationDesign of Low Power Wake-up Receiver for Wireless Sensor Network
Design of Low Power Wake-up Receiver for Wireless Sensor Network Nikita Patel Dept. of ECE Mody University of Sci. & Tech. Lakshmangarh (Rajasthan), India Satyajit Anand Dept. of ECE Mody University of
More informationDesign Of Low Power Cmos High Performance True Single Phase Clock Dual Modulus Prescaler
RESEARCH ARTICLE OPEN ACCESS Design Of Low Power Cmos High Performance True Single Phase Clock Dual Modulus Prescaler Ramesh.K 1, E.Velmurugan 2, G.Sadiq Basha 3 1 Department of Electronics and Communication
More informationLow Power and High Performance ALU using Dual Mode Transmission Gate Diffusion Input (DMTGDI)
International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 8958, Volume-6 Issue-6, August 2017 Low Power and High Performance ALU using Dual Mode Transmission Gate Diffusion Input
More information! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology. " Gate choice, logical optimization. " Fanin, fanout, Serial vs.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Design Space Exploration Lec 18: March 28, 2017 Design Space Exploration, Synchronous MOS Logic, Timing Hazards 3 Design Problem Problem Solvable!
More informationDesign and Implementation of Digital CMOS VLSI Circuits Using Dual Sub-Threshold Supply Voltages
RESEARCH ARTICLE OPEN ACCESS Design and Implementation of Digital CMOS VLSI Circuits Using Dual Sub-Threshold Supply Voltages A. Suvir Vikram *, Mrs. K. Srilakshmi ** And Mrs. Y. Syamala *** * M.Tech,
More information12-nm Novel Topologies of LPHP: Low-Power High- Performance 2 4 and 4 16 Mixed-Logic Line Decoders
12-nm Novel Topologies of LPHP: Low-Power High- Performance 2 4 and 4 16 Mixed-Logic Line Decoders Mr.Devanaboina Ramu, M.tech Dept. of Electronics and Communication Engineering Sri Vasavi Institute of
More informationA 2-bit/step SAR ADC structure with one radix-4 DAC
A 2-bit/step SAR ADC structure with one radix-4 DAC M. H. M. Larijani and M. B. Ghaznavi-Ghoushchi a) School of Engineering, Shahed University, Tehran, Iran a) ghaznavi@shahed.ac.ir Abstract: In this letter,
More informationr 2 ISSN Multiplier can large product bits in operation. process for Multiplication In is composed adder carry and of Tree Multiplier
Implementation Comparison of Tree Multiplier using Different Circuit Techniques Subhag Yadav, Vipul Bhatnagar, Department of Electronics Communication, Inderprastha Engineering College, UPTU, Ghaziabad,
More informationDesign and Implementation of combinational circuits in different low power logic styles
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 6, Ver. II (Nov -Dec. 2015), PP 01-05 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Design and Implementation of
More informationChapter 3 DESIGN OF ADIABATIC CIRCUIT. 3.1 Introduction
Chapter 3 DESIGN OF ADIABATIC CIRCUIT 3.1 Introduction The details of the initial experimental work carried out to understand the energy recovery adiabatic principle are presented in this section. This
More informationDesign and Implementation of Low Power Dynamic Thermometer Encoder For Flash ADC
Design and Implementation of Low Power Dynamic Thermometer Encoder For Flash ADC Abstract: In the design of a low power Flash ADC, a major challenge lies in designing a high speed thermometer code to binary
More informationUltra Low Power Consumption Military Communication Systems
Ultra Low Power Consumption Military Communication Systems Sagara Pandu Assistant Professor, Department of ECE, Gayatri College of Engineering Visakhapatnam-530048. ABSTRACT New military communications
More informationCOMPARATIVE ANALYSIS OF PULSE TRIGGERED FLIP FLOP DESIGN FOR LOW POWER CONSUMPTION
DOI: 10.21917/ijme.2018.0102 COMPARATIVE ANALYSIS OF PULSE TRIGGERED FLIP FLOP DESIGN FOR LOW POWER CONSUMPTION S. Bhuvaneshwari and E. Kamalavathi Department of Electronics and Communication Engineering,
More informationA New High Speed - Low Power 12 Transistor Full Adder Design with GDI Technique
International Journal of Scientific & Engineering Research Volume 3, Issue 7, July-2012 1 A New High Speed - Low Power 12 Transistor Full Design with GDI Technique Shahid Jaman, Nahian Chowdhury, Aasim
More informationInternational Journal of Electronics and Communication Engineering & Technology (IJECET), INTERNATIONAL JOURNAL OF ELECTRONICS AND
INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) ISSN 0976 6464(Print) ISSN 0976 6472(Online) Volume 4, Issue 3, May June, 2013, pp. 24-32 IAEME: www.iaeme.com/ijecet.asp
More informationAN EFFICIENT ADIABATIC FULL ADDER DESIGN APPROACH FOR LOW POWER
AN EFFICIENT ADIABATIC FULL ADDER DESIGN APPROACH FOR LOW POWER Baljinder Kaur 1, Narinder Sharma 2, Gurpreet Kaur 3 1 M.Tech Scholar (ECE), 2 HOD (ECE), 3 AP(ECE) ABSTRACT In this paper authors are going
More informationCMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits
Lec Sequential CMOS Logic Circuits Sequential Logic In Combinational Logic circuit Out Memory Sequential The output is determined by Current inputs Previous inputs Output = f(in, Previous In) The regenerative
More informationClassification of Digital Circuits
Classification of Digital Circuits Combinational logic circuits. Output depends only on present input. Sequential circuits. Output depends on present input and present state of the circuit. Combinational
More informationLOW POWER NOVEL HYBRID ADDERS FOR DATAPATH CIRCUITS IN DSP PROCESSOR
LOW POWER NOVEL HYBRID ADDERS FOR DATAPATH CIRCUITS IN DSP PROCESSOR B. Sathiyabama 1, Research Scholar, Sathyabama University, Chennai, India, mathumithasurya@gmail.com Abstract Dr. S. Malarkkan 2, Principal,
More informationA new 6-T multiplexer based full-adder for low power and leakage current optimization
A new 6-T multiplexer based full-adder for low power and leakage current optimization G. Ramana Murthy a), C. Senthilpari, P. Velrajkumar, and T. S. Lim Faculty of Engineering and Technology, Multimedia
More informationISSN Vol.04, Issue.05, May-2016, Pages:
ISSN 2322-0929 Vol.04, Issue.05, May-2016, Pages:0332-0336 www.ijvdcs.org Full Subtractor Design of Energy Efficient, Low Power Dissipation Using GDI Technique M. CHAITANYA SRAVANTHI 1, G. RAJESH 2 1 PG
More informationDesign of Two High Performance 1-Bit CMOS Full Adder Cells
Int. J. Com. Dig. Sys. 2, No., 47-52 (23) 47 International Journal of Computing and Digital Systems -- An International Journal @ 23 UOB CSP, University of Bahrain Design of Two High Performance -Bit CMOS
More informationAdiabatic Logic Circuits for Low Power, High Speed Applications
IJSTE - International Journal of Science Technology & Engineering Volume 3 Issue 10 April 2017 ISSN (online): 2349-784X Adiabatic Logic Circuits for Low Power, High Speed Applications Satyendra Kumar Ram
More informationDesign of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders
Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders B. Madhuri Dr.R. Prabhakar, M.Tech, Ph.D. bmadhusingh16@gmail.com rpr612@gmail.com M.Tech (VLSI&Embedded System Design) Vice
More informationParallel Self Timed Adder using Gate Diffusion Input Logic
IJSTE - International Journal of Science Technology & Engineering Volume 2 Issue 4 October 2015 ISSN (online): 2349-784X Parallel Self Timed Adder using Gate Diffusion Input Logic Elina K Shaji PG Student
More informationDesign of an Energy Efficient, Low Power Dissipation Full Subtractor Using GDI Technique
Design of an Energy Efficient, Low Power Dissipation Full Subtractor Using GDI Technique ABSTRACT: Rammohan Kurugunta M.Tech Student, Department of ECE, Intel Engineering College, Anantapur, Andhra Pradesh,
More informationSophisticated design of low power high speed full adder by using SR-CPL and Transmission Gate logic
Scientific Journal of Impact Factor(SJIF): 3.134 International Journal of Advance Engineering and Research Development Volume 2,Issue 3, March -2015 e-issn(o): 2348-4470 p-issn(p): 2348-6406 Sophisticated
More informationDesign Of A Comparator For Pipelined A/D Converter
Design Of A Comparator For Pipelined A/D Converter Ms. Supriya Ganvir, Mr. Sheetesh Sad ABSTRACT`- This project reveals the design of a comparator for pipeline ADC. These comparator is designed using preamplifier
More informationDesign & Simulation of Half Adder Circuit Using AVL technique based on CMOS Technology
Design & Simulation of Half Adder Circuit Using AVL technique based on CMOS Technology Mateshwar Singh1, Surya Deo Choudhary 2, Ashutosh kr.singh3 1M.Tech Student, Dept. of Electronics & Communication,
More informationDesign of Adaptive Triggered Flip Flop Design based on a Signal Feed-Through Scheme
Design of Adaptive Triggered Flip Flop Design based on a Signal Feed-Through Scheme *K.Lavanya & **T.Shirisha *M.TECH, Dept. ofece, SAHASRA COLLEGE OF ENGINEERING FOR WOMEN Warangal **Asst.Prof Dept. of
More informationPass Transistor and CMOS Logic Configuration based De- Multiplexers
Abstract: Pass Transistor and CMOS Logic Configuration based De- Multiplexers 1 K Rama Krishna, 2 Madanna, 1 PG Scholar VLSI System Design, Geethanajali College of Engineering and Technology, 2 HOD Dept
More informationImplementation of Carry Select Adder using CMOS Full Adder
Implementation of Carry Select Adder using CMOS Full Adder Smitashree.Mohapatra Assistant professor,ece department MVSR Engineering College Nadergul,Hyderabad-510501 R. VaibhavKumar PG Scholar, ECE department(es&vlsid)
More informationDesign of High Performance Arithmetic and Logic Circuits in DSM Technology
Design of High Performance Arithmetic and Logic Circuits in DSM Technology Salendra.Govindarajulu 1, Dr.T.Jayachandra Prasad 2, N.Ramanjaneyulu 3 1 Associate Professor, ECE, RGMCET, Nandyal, JNTU, A.P.Email:
More informationA NOVEL 4-Bit ARITHMETIC LOGIC UNIT DESIGN FOR POWER AND AREA OPTIMIZATION
A NOVEL 4-Bit ARITHMETIC LOGIC UNIT DESIGN FOR POWER AND AREA OPTIMIZATION Mr. Snehal Kumbhalkar 1, Mr. Sanjay Tembhurne 2 Department of Electronics and Communication Engineering GHRAET, Nagpur, Maharashtra,
More informationDesign of Low Power High Speed Hybrid Full Adder
IJECT Vo l. 6, Is s u e 4, Oc t - De c 2015 ISSN : 2230-7109 (Online) ISSN : 2230-9543 (Print) Design of Low Power High Speed Hybrid Full Adder 1 P. Kiran Kumar, 2 P. Srikanth 1,2 Dept. of ECE, MVGR College
More informationA Novel Hybrid Full Adder using 13 Transistors
A Novel Hybrid Full Adder using 13 Transistors Lee Shing Jie and Siti Hawa binti Ruslan Department of Electrical and Electronic Engineering, Faculty of Electric & Electronic Engineering Universiti Tun
More informationOptimization of Digitally Controlled Oscillator with Low Power
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 6, Ver. I (Nov -Dec. 2015), PP 52-57 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Optimization of Digitally Controlled
More informationADVANCES in NATURAL and APPLIED SCIENCES
ADVANCES in NATURAL and APPLIED SCIENCES ISSN: 1995-0772 Published BYAENSI Publication EISSN: 1998-1090 http://www.aensiweb.com/anas 2017 Special 11(6): pages 599-604 Open Access Journal Design A Full
More informationCMOS Digital Integrated Circuits Analysis and Design
CMOS Digital Integrated Circuits Analysis and Design Chapter 8 Sequential MOS Logic Circuits 1 Introduction Combinational logic circuit Lack the capability of storing any previous events Non-regenerative
More informationD Flip Flop with Different Technologies
Adv. Eng. Tec. Appl. 3, No. 1, 1-6 (2014) 1 Advanced Engineering Technology and Application An International Journal http://dx.doi.org/10.12785/aeta/paper D Flip Flop with Different Technologies Amit Grover
More informationA Novel Low power and Area Efficient Carry- Lookahead Adder Using MOD-GDI Technique
A Novel Low power and Area Efficient Carry- Lookahead Adder Using MOD-GDI Technique Pinninti Kishore 1, P. V. Sridevi 2, K. Babulu 3, K.S Pradeep Chandra 4 1 Assistant Professor, Dept. of ECE, VNRVJIET,
More informationPreface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate
Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation
More informationLow Power 6-Transistor Latch Design for Portable Devices
Low Power 6-Transistor Latch Design for Portable Devices Abhilasha 1, *K.G.Sharma 2, Tripti Sharma 2 and Prof.B.P.Singh 1 Deptt. of Electronics and Communication Engg., FET-MITS Lakshmangarh, Rajasthan
More information