Dynamic Logic. Domino logic P-E logic NORA logic 2-phase logic Multiple O/P domino logic Cascode logic 11/28/2012 1

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1 Dynamic Logic Dynamic Circuits will be introduced and their performance in terms of power, area, delay, energy and AT 2 will be reviewed. We will review the following logic families: Domino logic P-E logic NORA logic 2-phase logic Multiple O/P domino logic Cascode logic 11/28/2012 1

2 A brief introduction to Dynamic logic Dynamic logic Steady-State Behavior of Dynamic Logic Performance of Dynamic Logic Noise Considerations in Dynamic Design 11/28/2012 2

3 Dynamic Latch: Charge Leakage Stored charge leaks away due to reverse-bias current. Stored value is good for about 1 ms. Value must be rewritten to be valid. If not loaded every cycle, otherwise it must be ensured that the latch is loaded often enough to keep data valid. D X Cd+Cg X 11/28/2012 3

4 Dynamic Latch-Operation Uses complementary transmission gate to ensure that storage node is always strongly driven. Latch is transparent when transmission gate is closed. Storage capacitance comes primarily from transmission gate diffusion capacitance and inverter gate capacitance. = 0: transmission gate is off, inverter output is determined by storage node. = 1: transmission gate is on, inverter output follows D input. Setup and hold times determined by transmission gate must ensure that value stored on transmission gate is solid. 11/28/2012 4

5 Dynamic Combinational Logic Precharge/ Evaluate Networks V DD V DD M p Out M p In 1 In 2 In 3 PDN C L In 1 In 2 In 3 PUN Out M e M e C L n network p network 11/28/2012 5

6 Example of Dynamic Circuit OUTPUT A B CLK C CLK OUTPUT Precharge Evaluation Precharge 11/28/2012 6

7 General Concept Precharge and Evaluation Mp precharge transistor OUTPUT A B CLK ф C Me Evaluation transistor CLK OUTPUT Precharge Evaluation Precharge Example of nmos block For OUTPUT= (A.B + C) 11/28/2012 7

8 Charge and discharge Clock, ф A B C Output 11/28/2012 8

9 Overcoming the charge leakage and the charge sharing Mp OUTPUT A B CLK ф Me C 11/28/2012 9

10 Example continue V DD M p Out N + 1 Transistors Ratioless No Static Power Consumption A B C Noise Margins small (NM L ) Requires Clock M e 11/28/

11 Charge Leakage 11/28/

12 Charge Sharing 11/28/

13 Clock Feed through 11/28/

14 Cascading Dynamic Logic 11/28/

15 V o u t ( V o l t ) Transient Response 6.0 V out 4.0 EVALUATION PRECHARGE e e e e-09 t (nsec) 11/28/

16 4 Input NAND V DD Out In 1 In 2 In 3 In 4 GND 11/28/ Prentice Hall/Rabaey

17 Dynamic Flip-Flop D X x Y Q X X Y Q 11/28/

18 P-E logic Instead of using a static invert to ensure that 0 to 1 transitions occur during precharge, we can exploit the duality between n- block and p-block. The precharge output value of n- block equals 1, which is the correct value for the input of a p-block during precharge. All PMOS transistors of the Pull-Up Network (PUN) are turned off, so, an erroneous discharge at the on set of the evaluation phase is prevented. In a similar way, an n- block can follow a p-block without any problem, as the precharge value of inputs equals 0. To make the evaluation and precharge times of the p and n-block coincide, one has to clock the p-block with an inverted clock p. 11/28/

19 PE Logic V DD V DD M p Out M p In 1 In 2 In 3 PDN C L In 1 In 2 In 3 PUN Out M e M e C L n network p network 11/28/

20 Domino logic A Domino logic module consists of a n block followed by a static inverter. This ensures that all inputs to the next logic block are set to 0 after the precharge periods. Hence, the only possible transition during the evaluation period is 0 to 1 transition, so that formulated rule is obeyed. 11/28/

21 The block of Domino logic 11/28/

22 One Bit full Adder-Domino 11/28/

23 Simulation Results 11/28/

24 Multiple O/P Domino Logic The main concept behind MODL is the utilization of sub-functions available in the logic tree of domino gates, thus saving replication of circuitry. The additional ouputs are obtained by adding precharge devices and static inverters at the corresponding intermediate nodes of the logic tree. 11/28/

25 Multiple Output Domino C 1 = G 1 + P 1 C 0 C 2 = G 2 + P 2 C1 C 3 = G 3 + P 3 C2 C 4 = G 4 + P 4 C3 Expanding the above in terms of C1,C2,C3: C 1 = G 1 + P 1 C 0 C 2 = G 2 + P 2 (G 1 + P 1 C 0) C 3 = G 3 + P 3 (G 2 + P 2 (G 1 + P 1 C 0)) C 4 = G 4 + P 4 (G3 + P 3 (G 2 + P 2 (G 1 + P 1 C 0))) Expanding it fully C 1 = G 1 + P 1 C 0 C 2 = G 2 + P 2 G 1 + P 2 P 1 C o C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 +P 3 P 2 P 1 C 0 C 4 = G 4 + P 4 G 3 + P 4 P 3 G 2 +P 4 P 3 P 2 G 1 + P 4 P 3 P 2 P 1 C 0 11/28/

26 Multiple output Domino 11/28/

27 MODL 4-bit Carry Block C 1 = G 1 + P 1 C 0 C 2 = G 2 + P 2 G 1 + P 2 P 1 C o 11/28/2012 C 3 = G 3 + P 3 G 2 + P 3 P 2 G 1 +P 3 P 2 P 1 C 0 27 C 4 = G 4 + P 4 G 3 + P 4 P 3 G 2 +P 4 P 3 P 2 G 1 + P 4 P 3 P 2 P 1 C 0

28 2-Phase Logic We can use two-phase clock to control logic transition similar to PE. A single clock (phi1 or phi2) is used to precharge and evaluate the logic block. The succeeding stage is operated on the opposite clock phase. A latch is needed between two stages. 11/28/

29 Ø1 Evaluation Precharge Evaluation Precharge Ø2 Evaluation Precharge Evaluation Precharge ф1 Ф2 Ф1 Ф2 From ф2 stage ф1 ф1 n-logic ф2 ф2 n-logic To ф1 stage Ф1 Ф2 11/28/

30 2-Phase Domino logic 11/28/

31 NORA Logic Combining C 2 MOS pipeline register and P-E CMOS dynamic logic function block, we get NORA-CMOS (mean NO-Race). The method is suitable for the implementation of pipelined datapaths. 11/28/

32 The block of NORA logic CMOS INVER TER 11/28/

33 Cascode Logic Further refinement leads to a clocked version of the CVSL gate. This is really just two Domino gates operating on the true and complement inputs with a minimized logic tree. The advantage of this style of logic over domino logic is the ability to generate any logic expression, making it a complete logic family. This is achieved at the expense of the extra routing, active area, and complexity associated with dealing-rail logic. 11/28/

34 CASCOD Logic 11/28/

35 Comparison of 8-bit Adders Designed with Dynamic Logic Seven circuits using six dynamic logic functions are designed and simulated. The performance in terms of power, area, delay, energy and AT 2 are compared. 11/28/

36 Dynamic Logic Adders that are designed and compared Domino logic 8-bit Adder P-E logic 8-bit Adder NORA logic 8-bit Adder 2-Phase Logic 8-bit Adder Multiple O/P Domino Logic 8-bit Adder Cascode Logic 8-bit Adder 11/28/

37 Power 11/28/

38 Area 11/28/

39 Delay 11/28/

40 DP 11/28/

41 AT 2 11/28/

42 Conclusion Domino Logic: It has minimum area and number of transistors. The power consumption is low, and the delay is the longest. The DP and AT 2 are average. If the design goal is minimum area and speed is a secondary concern the Domino logic is the best structure for Ripple Carry Adder. 11/28/

43 Conclusion. P-E Logic: has a small area and the minimum number of transistors. The power consumption is low, and the delay is short. It has the lower DP and AT 2 for Ripple Carry Adder. If the logic has no inherent race problem, it will be the best choice for Ripple Carry Adder. 11/28/

44 Conclusion. P-E (race-free) Logic: In order to avoid the race condition of P-E Logic, the P-E (racefree) Logic is introduced. It has a small area and average of number of the transistors. The area and number of transistors is larger than P-E logic. The power consumption is average. The delay is shortest. It has lower DP and AT 2 for Ripple Carry Adder. For synthesis, it is the best choice for Ripple Carry Adder. 11/28/

45 Conclusion. NORA Logic: The power consumption is higher. The area is small, and using a few transistors except Domino logic. The delay is longer. The DP is high and AT 2 are average. 11/28/

46 Conclusion. 2-Phase Logic: The area is larger and the number of transistors is more than others except Cascode logic. The delay is longer. The power consumption, DP and AT 2 are extremely high. Try to avoid this logic structure for designing Ripple Carry Adder. 11/28/

47 Dynamic Circuits: Advantages & Disadvantages Advantages: Circuits occupy less area than the static circuits Circuits Operate at higher speed than static CMOS Circuits are Noise sensitive Drawbacks: Affected by charge sharing and charge re- distribution Always require clocks Cannot operate at low frequency Design is not straight forward 11/28/

48 FINAL WORD Thank you for being good students. I hope you have learned something in this class, that it will be useful in your future endeavor. Always go to the root of any problem that you are solving, whether engineering or social. Be a Good engineer, Never forget your Engineering ethics. Always keep your mind open to new ideas and development, and have vision as were the world is heading and try to be there before others. Do NOT forget the environment. Be a team player. Always be a dignified Engineer, respect yourself and other people s dignity. Be just to yourself and give justice to others. Always 11/28/2012 Have good intentions with your thinking, 48 actions and speaking. THANK YOU

49 Ф1 ф2 ф1 ф2 From ф2 stage Ф1 block Ф1 ф2 Ф2 block To ф1 stages Ф Ф1 ф2 11/28/

50 2-phase domino logic 11/28/