Low Power Design. Prof. MacDonald

Transcription

1 Low Power Design Prof. MacDonald

2 Power the next challenge! l High performance thermal problems power is now exceeding watts l difficult to remove heat from system l slows down circuits - mobilities l affects reliability (electromigration, hot carriers get worse) l Battery Applications battery-powered electronics growing exponentially l remote sensors, mp3 players, cell phones battery technology improves slowly compared to electronics more power results in less battery life

3 Packaging and thermal resistance! l Must design circuits to min and max junction temp l Junction temp Ambient temp plus heat from circuit l Circuit heat Power times theta J of the package l Some packages are better than others plastic have high theta J 40 C/W ceramic is better (10-20 C/W) but more expensive T j T + θ a j P

4 Packaging and thermal resistance! l So if a chip has the following requirements/constraints 500 Mhz operation, Tamax 65C Power estimated to be 1 watt Plastic quad flat pack package with theta J of 40 C/W l then the chip should run at 500MHz at 105 C. T j T + θ a j P

5 Metrics power * delay product! Pavg V 2 f C tp 2 1 f PDP Pavg tp V 2 C 2

6 Metrics energy * delay product! EDP PDP tp dv ΔV t p C C dt I C 2 3 V EDP 2 K ( V V ) t

7 Dynamic Power! l Dynamic Power capacitance charging / discharging power is proportional to number of logical transitions frequency and activity level increase power also includes l short circuit power PFET and NFET on simultaneously l some analog circuits always draw power reference voltages, etc Pd α V 2 f C

8 Dynamic Power - frequency! l Reducing frequency is generally not an option l frequency affects performance unless performance can be reduced, don t lower frequency some applications can identify low load times and scale down temporarily Pd α V 2 f C

9 Dynamic Power - capacitance! l Reducing capacitance means either lowering the cap per transistor and average cap overall l this is what happens with each technology shrink reducing the number of transistors (less functionality) C t C g W i L i Pd α V 2 f C

10 Dynamic Power activity level! l Reducing activity level is the best weapon against power for a given technology and frequency gate clocks that are not being used minimize transitions in combinational circuits minimize glitches gate unnecessary transitions Pd α V 2 f C

11 Dynamic Power voltage! l due to the quadratic relationship with power, voltage is the biggest hammer against power however voltage affects performance as well (1/x relationship) if performance requirements aren t constant, dynamic scaling l lower frequency when load is light l lower voltage as low as new frequency allows l 1/10 frequency and ½ voltage means 40 times less power at 1/10 performance much more energy efficient. Pd α V 2 f C

12 Dynamic Power shoot-through! l Some duration where both pull up and pull down networks are simultaneously on. shoot-through current, crow bar current l Combat this with short transition times and no overloaded nodes both conditions are checked for every net on a chip example limits might be 500ns of rise or fall time. l High transition times are a problem when scaling voltage. At low voltage devices slow down and transition times sky-rocket.

13 Dynamic Power clock tree! l Clock tree is 20-40% of total dynamic power l Most active net in chip twice as fast as data l Clock tree drives thousands (millions) of flops each flop has in the tens of ff clock load intermediate levels of clock tree have pf total tree might have 100 s of pf of load (and is most active) l Gate sections of tree for logic not currently being used

14 Static Power! l static power is now over half the power particularly for technologies 90nm and below l previously, static power was negligible l two main forms of static power today sub-threshold leakage classic static power l doubles every 11 degrees C l increases linearly with voltage gate leakage new leakage due to thin oxides (20A) l insensitive to temperature l due to quantum tunneling

15 Static Power - subthreshold! l typical subthreshold leakage high performance transistor 1nA/um low power transistor 1pA/um l for a chip with 100 million transistors with an average width of 10 um, total width of 1 billion um. l for high performance 1na/um * 1 km 1 amp of current l for low power 1pa/um * 1km 1 ma

16 Static Power - subthreshold and Vts! Ids(log) more Ion faster Ionf Ions Iofff less Ioff less static power Ioffs Vtf Vts Vgs

17 Static Power back-biasing! l Apply supply values to wells for standard operation l provide a negative voltage to raise Vt and lower subthreshold leakage slow but less static power l provide a positive voltage to reduce Vt and increase performance fast but leaks like a sieve can only go forward by one potential drop or source / body junction will be forward biased

18 Static Power gate oxide! l tunneling takes off below 20 angstroms of gate oxide thickness (90nm technology and below) l 20 amps per square centimeter of chip area l Avoid by creating an oxide that is mechanically thicker (> 20 Angstroms), while simultaneously electrically thinner (better channel control) need different materials to change dielectric constant l Temperature insensitive l Voltage sensitive

19 Footer / Header Transistors! low vt circuit idle N1 virtual ground ground

20 Clock Gating! l Turn off clocks to flops not changing l Dangerous avoid clipping clock glitch l Gate with latch to condition enable l Can gate a clock to idle logic core l Can gate a clock to small group of flops

21 Clock Gating! transparent latch, gate clk, den and outenc one of the only reasons to use a latch in logic CLKN transparent transparent transparent hold hold hold en enc time

22 Glitch Reduction! l Avoid timing through combinational logic that causes temporary false outputs l Each glitch results in two transitions unnecessarily l Can be handled with logic synthesis

23 Multi-threshold Design! l Use low Vts devices only in critical path l High Vt devices for all other gates l Best compromise between fast, leaky transistors for critical path slow transistors for everything else l Dual Vt process costs more Need two Vt implants one extra step l What about designs with 1000 s of almost critical paths?