Combinational Logic. Prof. MacDonald

Transcription

1 Combinational Logic Prof. MacDonald

2 2 Input NOR depletion NFET load l Pull Down Network can pull OUT down if either or both inputs are above Vih consequently the NOR function. l Depletion NFET could really be any load. Vdd Out

3 2 Input NOR depletion NFET load l If both and are low (<VIL) load charges OUT high Vdd Out

4 Parallel Transistor Configurations l Two same-type transistors in parallel have their transconductances added if on at same time. l If both transistors are on simultaneously and the L values are the same for both, we can add the widths to get an effective single transistor equivalent. l When both are on, (W/L)eq is sum of all ratios 8/1 8/1 16/1

5 Series Transistor Configurations (W/L)eq = (W/L)a + (W/L)b or if Ls equal, simply add Ws W W L L W L

6 Series Transistor Configurations l Two same-type transistors in series have their resistances added if on at same time. l If both transistors are on simultaneously and the W values are the same for both, we can add the lengths to get an effective single transistor equivalent. 8/1 8/2 = 4/1 8/1

7 Series Transistor Configurations (W/L)eq = 1 / (sum of reciprocals) or if Ws are equal, simply add Ls W L W L

8 2 Input NOR depletion NFET load If both and is high NFET heavy inverter Vdd Out

9 Noise Margins Voh = Vdd Vol depends on which driver(s) is on worst-case? Vih and Vil calculated as inverter Vdd Out

10 Power Worst-case is and high. Idload = Ida + Idb for static power Dynamic power (charging/discharging cap) the same for all cases. Vdd Out

11 Generalized Depletion NOR Can increase inputs to any value (theoretically). What is the limit? Vdd Out C

12 2 Input Depletion NND Only when both transistors ( and ) are on will the output be driven low out =!( & ) Vdd

13 2 Input Depletion NND Since transistors are in series, the equivalent pull down transistor (assuming the two are the same) is (W/2L). Vdd

14 Depletion NNDs and body effect Consider the case where is held on, but the gate of transitions from low to high. The intermediate node will be at a non-zero value at the beginning. Vbs!= 0. Vdd intermediate node

15 Depletion NNDs and diffusion cap Consider the case where is held on, but the gate of transitions from low to high. The intermediate node will be at a non-zero value at the beginning. Vbs!= 0. Vdd diffusion cap may or may not already be charged when output transitions from high to low. This varies delay.

16 Generalized Depletion NNDs Can have more than two inputs but cap and body effect get worse. Vdd C

17 CMOS NNDS and NOR Consider transistor sizings for balanced circuits out out

18 NND Layout vdd n-well Legend active area metal 1 OUT poly gnd

19 CMOS NOR Transistor sizing Consider transistor sizings for balanced circuits W*4 W*4 W*2 out W W W out

20 CMOS NND Transistor Sizing Consider transistor sizings for balanced circuits 2*W 2*W 2*W 2*W out W out 2*W

21 CMOS NND Transistor Sizing Consider transistor sizings for balanced circuits C 2*W 3*W 3*W out W out C 3*W

22 Fanin (number of inputs) There is a limit to the number of inputs that can be used. C D E C D E

23 Fanout (number and/or size of loads) There is a limit to the number of gates that can be driven.

24 Fanout (number and/or size of loads) Small gates (widths) struggle to drive large gates due to capacitance. Typically, synthesis limits the fanout to 20 or less.

25 NND VTC Vout One input only Inverter out oth inputs Vin

26 Complex CMOS Logic Can make single stage gates that implement: ND-OR-Inverter (OI) OR-ND-Inverter (OI) Given a function F = ((*)+C) Invert the function to get N network F = (*)+C Take dual of N network equation to get PFET network F d = ( + )*C Remember that PFETs invert inputs naturally

27 Conversion to NND-NND logic f = abc + ab c + acd ND OR logic (f ) = ((abc + ab c + acd) ) Double inversion f = ((abc ) (ab c) (acd) ) NND - NND

28 NND-NND Conversion f = abc + ab c + acd f = ((abc ) (ab c) (acd) )

29 Conversion to NOR-NOR logic f = (a+b+c )(a+b +c)(a+c+d) OR-ND logic (f ) = (((a+b+c )(a+b +c)(a+c+d)) ) Double inversion f = ((a+b+c ) +(a+b +c) +(a+c+d) ) NOR-NOR

30 NOR-NOR Conversion (a+b+c )(a+b +c)(a+c+d) ((a+b+c ) +(a+b +c) +(a+c +d) )

31 Multi-level Conversion to NND e d c b a e a d c b

32 lternative Gate Symbols ( * ) + ( + ) *

33 lternative Gate Symbols ( * ) + ( + ) *

34 ubble conversion g f e d c b a

35 ubble conversion - step one g f e d c b a Invert OR gate inputs (converting to NND) Invert ND gate outputs (converting to NND)

36 ubble conversion - step two g f b e d c a Ensure all inversions come in pairs (canceling each other out) (i.e. invert input literals or add inverters)

37 ubble conversion - step three g f b e d c a Replace all Inverted-input OR gates with NND gates

38 Complex CMOS Logic C C PFET network out out C C NFET network

39 Complex CMOS - Equivalent Inverter C For pull down, the equivalent pull down strength (W/L ratio) has three cases: and on W/Leq = 1 / (1/(W/La) + 1/(W/Lb) C only W/Lc or all three W/Leq = W/Lc + 1 / (1/(W/La) + 1/(W/Lb) out C

40 Complex CMOS Logic - Euler C C C out C NFET network PFET network Find common Euler path which does not traverse any branch more than once.

41 Complex CMOS Logic Given a function F = ((*)+C) what is best layout to share diffusions when possible. One solution but not Vdd best nwell active area out active area in pwell Gnd C

42 Complex CMOS Logic Given a function F = ((*)+C) what is best layout to share diffusions when possible. Switch S/D of C for Vdd better. out Gnd C

43 Pass Gates In most static CMOS, a PFET network pulls high and a dual NFET network pulls low. In a pass gate configuration, they tie inputs to outputs. Pass gates can either be ON and pass a value or be OFF and tri-state an output. One NFET can do this, but passes high values poorly. One PFET can do this too, but passes low values poorly. in out enable

44 Pass Gates Couple of problems, not only will it not drive a full logic high, the effective R skyrockets to infinity as you approach Vdd-Vt. This means that it also slows down as well as and provides no drive strength when statically high, thus the output is susceptible to coupling noise. in out enable

45 Charge Sharing (and Pass Gates) Common interview question asis for DRM operation. t t=0, the gate is low, C1 (50 ff) is charged to 2 volts, C2 (25 ff) is charged to 3 volts. Later, the gate is turned on. What is voltage of C1 and C2? Simple Eng101, but most grads can t do it. v1 v2 C1 C2 gate

46 Complementary Transmission Gates Use a PFET and NFET in parallel, passes ones and zeros. Never used by logic designers, circuit designers hide them. TGs act as switches, either providing a resistive short or an open circuit. Does not provide drive, attenuating the signal. Susceptible to above Vdd or below Gnd noise at input.

47 Noise problems with TGs Consider the case where the TG is off, but the input is capacitively coupled down from 0 to 2*Vt. Then Vgs > Vt and the NFET will turn on momentarily. Consider the case where the TG is off, but the input is capacitively coupled up from Vdd to Vdd + 2*Vt. Then Vgs > Vt and the PFET will turn on momentarily. Morale of the story, never let a global signal drive a source, only the transistor gate.

48 Effective Resistance of TGs For passing low values, the NFET is fully on. For passing high values, the PFET is fully on. The effective resistance stays relatively constant regardless of the input voltage (as opposed to how pass gates respond). Vt Vdd-Vt Reff NFET R Combination PFET R Vin Vdd

49 Textbook Transmission Gate Mux d1 out d0 s Referred to as soft node Usually limited to 5 or 6 TGs.

50 Real Transmission Gate Mux d1 out d0 s Need input inverters for noise and output inverter to cancel inversion and provide drive strength

51 TG Logic b c a b c f b c Implements F = * + C

52 NFET Pass Gate Logic b b a f Implements F = ^ a Couple of major problems though: 1) really needs 4 transistors to get both complements, 2) if F is high, you ll have a Vt drop (slow and consumes power) 3) inputs are unbuffered to source (noise).

53 CPL Logic a b b f f a a b b f f a Implements F = ^

54 Full dder Cell l Very common circuit in processors l Slow and large (compared to NNDs) l Complete macro cell adds two 1 bit numbers provides 1 bit sum and carry out l Many can be connected together S = ^^C Cout = + C + C Cin S Cout

55 Full dder Cell C in S Cin S Cout C out

56 Ripple Carry dder 4 4 [3:0] [3:0] a b a b a b a b c out s c in full adder c out s c in full adder c out s c in full adder c out s c in full adder 0 5 Sum[4:0]

57 dder/subtracter 4 4 [3:0] [3:0] subtract a b a b a b a b c out s c in full adder c out s c in full adder c out s c in full adder c out s c in full adder 5 Sum[4:0]

58 Standard CMOS Full dder Cin I1 I3 I2 I4 I5 I6 N N I11 I12 I15 I16 I13 I14 CinN N Full Standard CMOS dder 40 transistors 20 PFETs / 20 NFET Delay Robust (even at low Vdd), Good Noise Immunity I7 I8 I17 I18 I9 I10 CoutN SumN I19 I20 I31 I32 Sum I21 I22 I23 Cin I25 I26 I27 I28 I33 Cout I34 I24 I29 I30

59 Transmission Gate dder Standard Transmission Gate dder 26 transistors - 13 PFET / 13 NFET I19 I20 I1 I2 I3 I4 Cin I9 I10 I11 I12 I13 I14 I15 I23 Sum I24 I21 I22 I5 I6 I16 I17 I18 I25 I26 Cout I7 I8

60 Complementary Pass Gate Logic N N CinN Cin N CinN Cin N I1 I2 I3 I4 N I15 I16 I17 I18 N I17 I18 I19 I20 Swing Restoring CPL dder 32 transistors 8 PFETs / 24 NFETs improved leakage over straight CPL Cin CinN I5 I7 I6 I13 I14 I8 I9 Sum I10 I11 SumN N I21 I23 I22 I31 I32 I24 I25 CoutN I26 I27 Cout I12 I28

61 LEN dder I1 I2 I7 I8 I9 I10 I3 I11 I12 I13 I14 Cin I4 I15 I16 I5 I17 I18 I6 I19 Sum I21 Cout Single Ended Pass Logic (LEN) dder 22 transistors - 5 PFETs / 17 NFETs highest density I20 I22