EMT 251 Introduction to IC Design. Combinational Logic Design Part IV (Design Considerations)

Transcription

1 EMT 251 Introduction to IC Design (Pengantar Rekabentuk Litar Terkamir) Semester II 2011/2012 Combinational Logic Design Part IV (Design Considerations)

2 Review : CMOS Inverter V DD tphl = f(rn, CL) V out tphl = 0.69 Reqn CL R n C L tphl = 0.69 (3/4 (CL VDD)/ IDSATn ) V in = V DD = 0.52 CL / (W/Ln k n VDSATn)

3 Review: Designing Fast CMOS Gates Transistor sizing Progressive transistor sizing FET closest to the output is smallest of series FETs Transistor ordering put latest arriving signal closest to the output Logic structure reordering replace large fan-in gates with smaller fan-in gate network Apply logical effort Buffer (inverter) insertion separate large fan-in from large CL with buffers uses buffers so there are no more than four TGs in series

4 Effect of Capacitive Loading When an input signal of a logic gate is changed, there is a propagation delay before the output of the logic gate changes. This is due to capacitive loading at the output. The propagation delay is measured between the 50% transition points of the input and output signals.

5 Propagation Delay in Timing Diagrams To simplify the drawing of timing diagrams, we can approximate the signal transitions to be abrupt (though in reality they are exponential).

6 Influence of Fan-In and Fan-Out on Delay Fan-in: the number of inputs of an electronic logic gate. For instance the fan-in for the AND gate shown below is 3. Physical logic gates with a large fan-in tend to be slower than those with a small fan-in, because the complexity of the input circuitry increases the input capacitance of the device Fan-out: the number of gate(s) that are connected to the output of the driving gate Fan-out leads to increased capacitive load on the driving gate, and therefore longer propagation delay

7 Calculating the propagation delay Model the MOSFET in the ON state as a resistive switch: Case 1: Vout changing from High to Low (input signal changed from Low to High) NMOSFET(s) connect Vout to GND

8 Calculating the Propagation Delay (cont d) Case 2: Vout changing from Low to High (input signal changed from High to Low) PMOSFET(s) connect Vout to VDD

9 Switch Delay Model A A R eq R p R p R p A B A R p B R n A R n B C L C int R n A INVERTER C L R n A A R p R n B C int C L NOR NAND

10 Input Pattern Effects on Delay A R p R n A R n B B R p C L C int Delay is dependent on the pattern of inputs Low to high transition both inputs go low delay is 0.69 Rp/2 CL since two p-resistors are on in parallel one input goes low delay is 0.69 Rp CL High to low transition both inputs go high delay is Rn CL Adding transistors in series (without sizing) slows down the circuit

11 Fan-In Considerations Distributed RC model (Elmore delay) tphl= 0.69 [R1C1+(R1+R2)C2+(R1+R2+R3)C3+(R1+R2+R3+R4)CL] tphl = 0.69 Reqn(C1+2C2+3C3+4CL) Propagation delay deteriorates rapidly as a function of fan-in quadratically in the worst case.

12 tp as a Function of Fan-In Gates with a fan-in greater than 4 should be avoided.

13 Fan-in Solution Alternative logic structures F = A.B.C.D.E.F.G.H

14 Transistor Sizing RESISTANCE: Requires balanced networks

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16 Transistor Sizing I The electrical characteristics of transistors determine the switching speed of a circuit Need to select the aspect ratios (W/L)n and (W/L)p of every FET in the circuit Define Unit Transistor (R1, C1) L/Wmin-> highest resistance (needs scaling) R2= R1 2 and C2= 2 C1 Separate nfet and pfet unit transistors Unit devices are not restricted to individual transistors

17 Sizing I : Complex Gates Critical Transistors: those in series N FETs in series => scale each by factor of N Ignore FETs in parallel (assume worst case: only 1 on) Ultimate goal: total resistance of net = 1 square

18 Sizing I : Complex Gates Critical Transistors: those in series N FETs in series => scale each by factor of N Ignore FETs in parallel (assume worst case: only 1 on) Ultimate goal: total resistance of net = 1 square

19 EXAMPLES 1

20 EXAMPLES 1

21 EXAMPLES 2

22 EXAMPLES 2

23 Ways to Improve Gate Delay Reduce CL internal diffusion capacitance of the gate itself (keep the drain diffusion as small as possible) other terms: interconnect capacitance & fanout Increase W/L ratio of the transistor the most powerful and effective performance optimization tool in the hands of the designer watch out for self-loading! when the intrinsic capacitance dominates the extrinsic load can trade-off energy for performance Increase VDD increasing VDD above a certain level yields only very minimal improvements reliability concerns enforce a firm upper bound on VDD

24 Sizing & Big Gates Sizing for Large Capacitive Loads Suppose Cload large (e.g. off-chip wires) Scale each inverter (both FETs in the circuit) by a factor A (input capacitances scale by A) if input C to last inverter * A = Cload (i.e., Cload looks like N+1th inverter) then we have: Input C of last inverter = Cin1*A*N = Cload Rearranging:

25 Sizing & Big Gates Sizing for Large Capacitive Loads Capacitances increase by factor of A left to right Resistances decrease by factor of A left to right total delay (tphl + tplh): Find optimal chain length:

26 Example Load is ~8000x that of single inverter s input capacitance: find optimal solution.

27 Example