CMOS VLSI Design (A3425)

Size: px
Start display at page:

Download "CMOS VLSI Design (A3425)"

Transcription

1 CMOS VLSI Design (A3425) Unit III Static Logic Gates Introduction A static logic gate is one that has a well defined output once the inputs are stabilized and the switching transients have decayed away. Static CMOS logic gates are relatively easy to design and use. This chapter deals with the static logic gates, from simple NAND and NOR operations to complex functions that are quite large and powerful. Communication Engineering 1

2 General Structure Static CMOS logic gates are constructed using completely symmetric nmos and pmos transistor arrays. Complex logic gates are constructed using the CMOS inverter as a basis. In order to construct a complex logic gate, let us replace the single inverter nfet by an array of nfets that are connected to operate as a large switch. Similarly, we will substitute an array of pfets for the single pfet used in the inverter, and view the pfet array as a giant switch. Steps to Create Complex Gates The general structure of a complex logic gate can be created by the following steps. Provide a complementary pair (an nfet and a pfet with a common gate) for each input; Replace the single nfet with an array of nfets that connects the output to ground; Replace the single pfet with an array of pfets that connects the output to V DD ; Design the nfet and pfet switching network so that only one network acts as a closed switch for any given input combination. Communication Engineering 2

3 General Structure of a Static Logic Gate Communication Engineering 3

4 Communication Engineering 4

5 Communication Engineering 5

6 Communication Engineering 6

7 Transient Analysis When analyzing the output transients, nfet and pfet to Logic Gate Equivalence Communication Engineering 7

8 Exclusive OR and Equivalence Gates Exclusive OR and Equivalence Gates Communication Engineering 8

9 Mirror Circuits The XOR operation is used extensively in several types of logic networks including adder circuits and parity checkers. The philosophy of mirror circuits can be better understood by considering a 2 variable gate. The possible input combinations are Since the XOR function has the form Mirror Circuits Since the XOR function has the form This means that the combinations should provide the connections from the output to the power supply, while should connect the output to ground. Similarly, the function for XNOR (Equivalence Gate) is Communication Engineering 9

10 Mirror Circuits Uses the same transistor topology for the nfet and pfet networks. When there are equal numbers of input combinations producing 0s and 1s. XOR XNOR Advantages: More symmetric layouts Shorter rise and fall times Mirror Circuits Communication Engineering 10

11 Mirror Circuits Mirror Circuits Communication Engineering 11

12 Communication Engineering 12

13 Full Adder Circuits Communication Engineering 13

14 NOR Based SR Latch NOR Based SR Latch Communication Engineering 14

15 Communication Engineering 15

16 SRAM Communication Engineering 16

17 SRAM Tri-State Output Circuits Static logic gates provide logic 0 and logic 1 output values by connecting the output node to either ground or to the power supply. Static Logic Two States - 0 and 1 A tri-state output circuit is designed to give these two logic states, but also provides for a third highimpedance (Hi-Z) state in which the output node is floating. Tri-State Output Logic Three States 0, 1 and Hi-Z Communication Engineering 17

18 Tri-State Output Circuits Figure shows tri-state circuit that uses the enable signal En to switch between normal and Hi-Z operation. pfet is controlled by the function nfet is controlled by the function If En=0, then fp=1, fn=0 which drives both FETs into cutoff, producing the Hi-Z state. If En=1, then fp=d, fn=d which allows the input D to control the transistors Tri-State Output Circuits Figure below reverses the roll of the tri-state control by moving the location of the inverter. The FET inputs are controlled by This results in the circuit that gives a Hi-Z output state when the control bit Hi is 1 and normal operation with Hi=0. Communication Engineering 18

19 Tri-State Output Circuits Figure below shows another tri-state circuit. In the circuit, the Hi-Z control variable X is applied directly to the tri-state pfet MpX while X is applied to MnX. If X=0, then both FETs are active and the gate produces an output of D. A Hi-Z state is achieved with X=1, since this turns both tri-state FETs OFF. Psuedo-nMOS Logic Gates nmos logic family uses only nfets Pseudo-nMOS logic resemble the nmos logic with active pull-up (pfet). Figure shows a basic nmos inverter A single nfet MD is a driver device that controls the circuit. The output node is connected to the power supply through a load resistor R L that acts as a pull-up device Communication Engineering 19

20 Psuedo-nMOS Logic Gates Operation For Vin<V Tn, the driver MD is in cutoff giving I D =0 Since the load current is equal to the driver current, the voltage across the load resistor is V L =I L R L = 0V The output voltage is given by Psuedo-nMOS Logic Gates Operation When a high input voltage V in = V DD is applied MD conducts but the resistor still tries to pull up the output voltage. This keeps V out from ever reaching 0V so that the output low voltage V OL is always greater than zero: V OL > 0. Psuedo-nMOS logic gate replaces the resistor with a biased-on pfet as shown in figure below. Communication Engineering 20

21 Psuedo-nMOS Logic Gates DC Characteristics and Operation pfet voltages are given by pfet is always biased into active region and cannot be turned off. For V in <V Tn, nfet is cutoff and V out = V DD = V OH For V in >V Tn, Mn turns into conduction, V in = V DD = V OH V OL is small Mn is non-saturated V OL < V Tp, Psuedo-nMOS Logic Gates driver-to-load ratio Communication Engineering 21

22 Complex Logic in Psuedo-nMOS Simplified XNOR Gate Communication Engineering 22

23 Compact XOR and Equivalence Gates Alternate XOR and XNOR Gates Communication Engineering 23

24 Alternate XOR and XNOR Gates Schmitt Trigger Circuits VTC exhibits hysteresis Forward characteristics are different from the reverse characteristics When Vin = 0V DD, the transition takes place at the forwardswitching voltage V +. When Vin = V DD 0, the transition takes place at the reverse switching voltage V -. The hysteresis voltage V H = V + -V - Communication Engineering 24

25 Schmitt Trigger Circuits A symmetrical CMOS Schmitt trigger circuit is shown in figure below. pfet circuit is the mirror image of the nfet circuit. The forward switching is controlled by the nfets while the reverse switching is determined by the pfets. Schmitt Trigger Circuits Forward switching voltage V + : Mn2 is the main switching device. Mn1 and Mn3 acts as feedback network which controls the value of V+. Assume that the input is set to Vin = 0 and then increased; all of nfets are initially in cutoff. Conduction depends on the gate-source voltages Mn1 turns ON when V GS1 =V T1 Mn2 requires an input voltage of Communication Engineering 25

26 Schmitt Trigger Circuits V+ can be estimated by ignoring body bias effects. To turn on Mn2 requires a drain-source voltage of Mn1 is in saturation with a current of Mn3 is also saturated (since V GS3 =V DS3 ) with a current of Equating current I 1 =I 3 and rearranging gives Similarly, the reverse trigger voltage V- is given by Schmitt Trigger Circuits Reverse switching voltage V - : Mp4 is in saturation with a current of Mp6 is also saturated with a current of Where V = V V γ Tp Equating I 4 =I 6 and rearranging gives I β 2 ( V ) 2 DD V VTp 4 4 = β 2 ( ) 2 γ 6 I6 = V V Tp Communication Engineering 26

27 Schmitt Trigger Circuits This CMOS circuit allows for designing a symmetric trigger where Hysteresis voltage is given by Alternate Schmitt Trigger Communication Engineering 27

Topic 6. CMOS Static & Dynamic Logic Gates. Static CMOS Circuit. NMOS Transistors in Series/Parallel Connection

Topic 6. CMOS Static & Dynamic Logic Gates. Static CMOS Circuit. NMOS Transistors in Series/Parallel Connection NMOS Transistors in Series/Parallel Connection Topic 6 CMOS Static & Dynamic Logic Gates Peter Cheung Department of Electrical & Electronic Engineering Imperial College London Transistors can be thought

More information

EEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic Families

EEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic Families EEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic Families Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Homework 5 this week Lab

More information

Electronic Circuits EE359A

Electronic Circuits EE359A Electronic Circuits EE359A Bruce McNair B206 bmcnair@stevens.edu 201-216-5549 1 Memory and Advanced Digital Circuits - 2 Chapter 11 2 Figure 11.1 (a) Basic latch. (b) The latch with the feedback loop opened.

More information

Digital Microelectronic Circuits ( ) CMOS Digital Logic. Lecture 6: Presented by: Adam Teman

Digital Microelectronic Circuits ( ) CMOS Digital Logic. Lecture 6: Presented by: Adam Teman Digital Microelectronic Circuits (361-1-3021 ) Presented by: Adam Teman Lecture 6: CMOS Digital Logic 1 Last Lectures The CMOS Inverter CMOS Capacitance Driving a Load 2 This Lecture Now that we know all

More information

Lecture 13. Biasing and Loading Single Stage FET Amplifiers. The Building Blocks of Analog Circuits - III

Lecture 13. Biasing and Loading Single Stage FET Amplifiers. The Building Blocks of Analog Circuits - III Lecture 3 Biasing and Loading Single Stage FET Amplifiers The Building Blocks of Analog Circuits III In this lecture you will learn: Current biasing of circuits Current sources and sinks for CS, CG, and

More information

Chapter 6 Combinational CMOS Circuit and Logic Design. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Chapter 6 Combinational CMOS Circuit and Logic Design. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Chapter 6 Combinational CMOS Circuit and Logic Design Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Advanced Reliable Systems (ARES) Lab. Jin-Fu Li,

More information

CMOS Digital Integrated Circuits Analysis and Design

CMOS Digital Integrated Circuits Analysis and Design CMOS Digital Integrated Circuits Analysis and Design Chapter 8 Sequential MOS Logic Circuits 1 Introduction Combinational logic circuit Lack the capability of storing any previous events Non-regenerative

More information

CMOS Circuits CONCORDIA VLSI DESIGN LAB

CMOS Circuits CONCORDIA VLSI DESIGN LAB CMOS Circuits 1 Combination and Sequential 2 Static Combinational Network CMOS Circuits Pull-up network-pmos Pull-down network-nmos Networks are complementary to each other When the circuit is dormant,

More information

Digital circuits. Bởi: Sy Hien Dinh

Digital circuits. Bởi: Sy Hien Dinh Digital circuits Bởi: Sy Hien Dinh This module presents the basic concepts of MOSFET digital logic circuits. We will examine NMOS logic circuits, which contain only n-channel transistors, and complementary

More information

Microelectronics Circuit Analysis and Design

Microelectronics Circuit Analysis and Design Microelectronics Circuit Analysis and Design Donald A. Neamen Chapter 3 The Field Effect Transistor Neamen Microelectronics, 4e Chapter 3-1 In this chapter, we will: Study and understand the operation

More information

Shorthand Notation for NMOS and PMOS Transistors

Shorthand Notation for NMOS and PMOS Transistors Shorthand Notation for NMOS and PMOS Transistors Terminal Voltages Mode of operation depends on V g, V d, V s V gs = V g V s V gd = V g V d V ds = V d V s = V gs - V gd Source and drain are symmetric diffusion

More information

ECE 3110: Engineering Electronics II Fall Final Exam. Dec. 16, 8:00-10:00am. Name: (78 points total)

ECE 3110: Engineering Electronics II Fall Final Exam. Dec. 16, 8:00-10:00am. Name: (78 points total) Final Exam Dec. 16, 8:00-10:00am Name: (78 points total) Problem 1: Consider the emitter follower in Fig. 7, which is being used as an output stage. For Q 1, assume β = and initally assume that V BE =

More information

CMOS VLSI Design (A3425)

CMOS VLSI Design (A3425) CMOS VLSI Design (A3425) Unit V Dynamic Logic Concept Circuits Contents Charge Leakage Charge Sharing The Dynamic RAM Cell Clocks and Synchronization Clocked-CMOS Clock Generation Circuits Communication

More information

CMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits

CMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits Lec Sequential CMOS Logic Circuits Sequential Logic In Combinational Logic circuit Out Memory Sequential The output is determined by Current inputs Previous inputs Output = f(in, Previous In) The regenerative

More information

Introduction to Electronic Devices

Introduction to Electronic Devices Introduction to Electronic Devices (Course Number 300331) Fall 2006 Dr. Dietmar Knipp Assistant Professor of Electrical Engineering Information: http://www.faculty.iubremen.de/dknipp/ Source: Apple Ref.:

More information

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. October 25, 2005

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. October 25, 2005 6.12 - Microelectronic Devices and Circuits - Fall 25 Lecture 13-1 Lecture 13 - Digital Circuits (II) MOS Inverter Circuits October 25, 25 Contents: 1. NMOS inverter with resistor pull-up (cont.) 2. NMOS

More information

Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology

Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology Kyung Ki Kim a) and Yong-Bin Kim b) Department of Electrical and Computer Engineering, Northeastern University, Boston, MA

More information

CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter. CMOS Inverter: A First Look

CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter. CMOS Inverter: A First Look CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic CMOS Inverter: A First Look C L 9/11/26 VLSI

More information

8. Combinational MOS Logic Circuits

8. Combinational MOS Logic Circuits 8. Combinational MOS Introduction Combinational logic circuits, or gates, witch perform Boolean operations on multiple input variables and determine the output as Boolean functions of the inputs, are the

More information

5. CMOS Gates: DC and Transient Behavior

5. CMOS Gates: DC and Transient Behavior 5. CMOS Gates: DC and Transient Behavior Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin VLSI Design Fall 2017 September 18, 2017 ECE Department, University

More information

Digital Electronics. Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region. Positive Logic.

Digital Electronics. Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region. Positive Logic. Digital Electronics Assign 1 and 0 to a range of voltage (or current), with a separation that minimizes a transition region Positive Logic Logic 1 Negative Logic Logic 0 Voltage Transition Region Transition

More information

Microelectronics Circuit Analysis and Design. MOS Capacitor Under Bias: Electric Field and Charge. Basic Structure of MOS Capacitor 9/25/2013

Microelectronics Circuit Analysis and Design. MOS Capacitor Under Bias: Electric Field and Charge. Basic Structure of MOS Capacitor 9/25/2013 Microelectronics Circuit Analysis and Design Donald A. Neamen Chapter 3 The Field Effect Transistor In this chapter, we will: Study and understand the operation and characteristics of the various types

More information

ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits

ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits Faculty of Engineering ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits CMOS Technology Complementary MOS, or CMOS, needs both PMOS and NMOS FET devices for their logic gates to be realized

More information

Gechstudentszone.wordpress.com

Gechstudentszone.wordpress.com UNIT 4: Small Signal Analysis of Amplifiers 4.1 Basic FET Amplifiers In the last chapter, we described the operation of the FET, in particular the MOSFET, and analyzed and designed the dc response of circuits

More information

55:041 Electronic Circuits

55:041 Electronic Circuits 55:041 Electronic Circuits Mosfet Review Sections of Chapter 3 &4 A. Kruger Mosfet Review, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width 1 10-6 m or less Thickness 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor

More information

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers Objective Design, simulate and layout various inverting amplifiers. Introduction Inverting amplifiers are fundamental building blocks of electronic

More information

Improved Inverter: Current-Source Pull-Up. MOS Inverter with Current-Source Pull-Up. What else could be connected between the drain and V DD?

Improved Inverter: Current-Source Pull-Up. MOS Inverter with Current-Source Pull-Up. What else could be connected between the drain and V DD? Improved Inverter: Current-Source Pull-Up MOS Inverter with Current-Source Pull-Up What else could be connected between the drain and? Replace resistor with current source I SUP roc i D v IN v OUT Find

More information

ECE/CoE 0132: FETs and Gates

ECE/CoE 0132: FETs and Gates ECE/CoE 0132: FETs and Gates Kartik Mohanram September 6, 2017 1 Physical properties of gates Over the next 2 lectures, we will discuss some of the physical characteristics of integrated circuits. We will

More information

UNIT-III GATE LEVEL DESIGN

UNIT-III GATE LEVEL DESIGN UNIT-III GATE LEVEL DESIGN LOGIC GATES AND OTHER COMPLEX GATES: Invert(nmos, cmos, Bicmos) NAND Gate(nmos, cmos, Bicmos) NOR Gate(nmos, cmos, Bicmos) The module (integrated circuit) is implemented in terms

More information

Chapter 13: Introduction to Switched- Capacitor Circuits

Chapter 13: Introduction to Switched- Capacitor Circuits Chapter 13: Introduction to Switched- Capacitor Circuits 13.1 General Considerations 13.2 Sampling Switches 13.3 Switched-Capacitor Amplifiers 13.4 Switched-Capacitor Integrator 13.5 Switched-Capacitor

More information

Chapter 6 DIFFERENT TYPES OF LOGIC GATES

Chapter 6 DIFFERENT TYPES OF LOGIC GATES Chapter 6 DIFFERENT TYPES OF LOGIC GATES Lesson 9 CMOS gates Ch06L9-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline CMOS (n-channel based MOSFETs based circuit) CMOS Features

More information

Combinational Logic Gates in CMOS

Combinational Logic Gates in CMOS Combinational Logic Gates in CMOS References: dapted from: Digital Integrated Circuits: Design Perspective, J. Rabaey UC Principles of CMOS VLSI Design: Systems Perspective, 2nd Ed., N. H. E. Weste and

More information

Lecture 14. FET Current and Voltage Sources and Current Mirrors. The Building Blocks of Analog Circuits - IV

Lecture 14. FET Current and Voltage Sources and Current Mirrors. The Building Blocks of Analog Circuits - IV Lecture 4 FET Current and oltage s and Current Mirrors The Building Blocks of Analog Circuits n this lecture you will learn: Current and voltage sources using FETs FET current mirrors Cascode current mirror

More information

CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4

CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 1 2 3 4 5 6 7 8 9 10 Sum 30 10 25 10 30 40 10 15 15 15 200 1. (30 points) Misc, Short questions (a) (2 points) Postponing the introduction of signals

More information

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 22, 2001

Lecture 13 - Digital Circuits (II) MOS Inverter Circuits. March 22, 2001 6.12 - Microelectronic Devices and Circuits - Spring 21 Lecture 13-1 Lecture 13 - Digital Circuits (II) MOS Inverter Circuits March 22, 21 Contents: 1. NMOS inverter with resistor pull-up (cont.) 2. NMOS

More information

MOS IC Amplifiers. Token Ring LAN JSSC 12/89

MOS IC Amplifiers. Token Ring LAN JSSC 12/89 MO IC Amplifiers MOFETs are inferior to BJTs for analog design in terms of quality per silicon area But MO is the technology of choice for digital applications Therefore, most analog portions of mixed-signal

More information

Digital Integrated CircuitDesign

Digital Integrated CircuitDesign Digital Integrated CircuitDesign Lecture 11 BiCMOS PMOS rray Q1 NMOS rray Y NMOS rray Q2 dib brishamifar EE Department IUST Contents Introduction BiCMOS Devices BiCMOS Inverters BiCMOS Gates BiCMOS Drivers

More information

PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Integrated Circuit Layers MOSFETs CMOS Layers Designing FET Arrays EE 432 VLSI Modeling and Design 2 Integrated Circuit Layers

More information

Depletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET

Depletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET Ch. 13 MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor : I D D-mode E-mode V g The gate oxide is made of dielectric SiO 2 with e = 3.9 Depletion-mode operation ( 공핍형 ): Using an input gate voltage

More information

ECE520 VLSI Design. Lecture 5: Basic CMOS Inverter. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 5: Basic CMOS Inverter. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 5: Basic CMOS Inverter Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture

More information

Digital Microelectronic Circuits ( ) Pass Transistor Logic. Lecture 9: Presented by: Adam Teman

Digital Microelectronic Circuits ( ) Pass Transistor Logic. Lecture 9: Presented by: Adam Teman Digital Microelectronic Circuits (361-1-3021 ) Presented by: Adam Teman Lecture 9: Pass Transistor Logic 1 Motivation In the previous lectures, we learned about Standard CMOS Digital Logic design. CMOS

More information

55:041 Electronic Circuits

55:041 Electronic Circuits 55:041 Electronic Circuits MOSFETs Sections of Chapter 3 &4 A. Kruger MOSFETs, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width = 1 10-6 m or less Thickness = 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor

More information

Digital Electronics Part II - Circuits

Digital Electronics Part II - Circuits Digital Electronics Part II - Circuits Dr. I. J. Wassell Gates from Transistors 1 Introduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits

More information

EE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad

EE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 23 p. 1/16 EE 42/100 Lecture 23: CMOS Transistors and Logic Gates ELECTRONICS Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad University

More information

CMOS LOGIC CIRCUIT DESIGN

CMOS LOGIC CIRCUIT DESIGN CMOS LOGIC CIRCUIT DESIGN CMOS LOGIC CIRCUIT DESIGN John P. Uyemura Georgia Institute of Technology KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW ebook ISBN: 0-306-47529-4 Print

More information

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

Radivoje Đurić, 2015, Analogna Integrisana Kola 1 OTA-output buffer 1 According to the types of loads, the driving capability of the output stages differs. For switched capacitor circuits which have high impedance capacitive loads, class A output stage

More information

D n ox GS THN DS GS THN DS GS THN. D n ox GS THN DS GS THN DS GS THN

D n ox GS THN DS GS THN DS GS THN. D n ox GS THN DS GS THN DS GS THN Name: EXAM #3 Closed book, closed notes. Calculators may be used for numeric computations only. All work is to be your own - show your work for maximum partial credit. Data: Use the following data in all

More information

電子電路. Memory and Advanced Digital Circuits

電子電路. Memory and Advanced Digital Circuits 電子電路 Memory and Advanced Digital Circuits Hsun-Hsiang Chen ( 陳勛祥 ) Department of Electronic Engineering National Changhua University of Education Email: chenhh@cc.ncue.edu.tw Spring 2010 2 Reference Microelectronic

More information

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate

Preface to Third Edition Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Preface to Third Edition p. xiii Deep Submicron Digital IC Design p. 1 Introduction p. 1 Brief History of IC Industry p. 3 Review of Digital Logic Gate Design p. 6 Basic Logic Functions p. 6 Implementation

More information

Module 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits

Module 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits Module 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits Objectives In this lecture you will learn the following Ratioed Logic Pass Transistor Logic Dynamic Logic Circuits

More information

VLSI Logic Structures

VLSI Logic Structures VLSI Logic Structures Ratioed Logic Pass-Transistor Logic Dynamic CMOS Domino Logic Zipper CMOS Spring 25 John. Chandy inary Multiplication + x Multiplicand Multiplier Partial products Result Spring 25

More information

4-bit counter circa bit counter circa 1990

4-bit counter circa bit counter circa 1990 Digital Logic 4-bit counter circa 1960 8-bit counter circa 1990 Logic gates Operates on logical values (TRUE = 1, FALSE = 0) NOT AND OR XOR 0-1 1-0 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1 0 1 0 1 1 1 1 1 0 0 0

More information

Homework Assignment 07

Homework Assignment 07 Homework Assignment 07 Question 1 (Short Takes). 2 points each unless otherwise noted. 1. A single-pole op-amp has an open-loop low-frequency gain of A = 10 5 and an open loop, 3-dB frequency of 4 Hz.

More information

CMOS Transistor and Circuits. Jan 2015 CMOS Transistor 1

CMOS Transistor and Circuits. Jan 2015 CMOS Transistor 1 CMOS Transistor and Circuits Jan 2015 CMOS Transistor 1 Latchup in CMOS Circuits Jan 2015 CMOS Transistor 2 Parasitic bipolar transistors are formed by substrate and source / drain devices Latchup occurs

More information

Chapter 6 DIFFERENT TYPES OF LOGIC GATES

Chapter 6 DIFFERENT TYPES OF LOGIC GATES Chapter 6 DIFFERENT TYPES OF LOGIC GATES Lesson 8 NMOS gates Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline NMOS (n-channel based MOSFETs based circuit) NMOS Features

More information

DIGITAL VLSI LAB ASSIGNMENT 1

DIGITAL VLSI LAB ASSIGNMENT 1 DIGITAL VLSI LAB ASSIGNMENT 1 Problem 1: NMOS and PMOS plots using Cadence. In this exercise, you are required to generate both NMOS and PMOS I-V device characteristics (I/P and O/P) using Cadence (Use

More information

Exam Below are two schematics of current sources implemented with MOSFETs. Which current source has the best compliance voltage?

Exam Below are two schematics of current sources implemented with MOSFETs. Which current source has the best compliance voltage? Exam 2 Name: Score /90 Question 1 Short Takes 1 point each unless noted otherwise. 1. Below are two schematics of current sources implemented with MOSFETs. Which current source has the best compliance

More information

Lecture 11 Digital Circuits (I) THE INVERTER

Lecture 11 Digital Circuits (I) THE INVERTER Lecture 11 Digital Circuits (I) THE INVERTER Outline Introduction to digital circuits The inverter NMOS inverter with resistor pull-up Reading Assignment: Howe and Sodini; Chapter 5, Sections 5.1-5.3 6.12

More information

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Ratioed Logic Introduction Digital IC EE141 2 Ratioed Logic design Basic concept Resistive load Depletion

More information

A Low Power Array Multiplier Design using Modified Gate Diffusion Input (GDI)

A Low Power Array Multiplier Design using Modified Gate Diffusion Input (GDI) A Low Power Array Multiplier Design using Modified Gate Diffusion Input (GDI) Mahendra Kumar Lariya 1, D. K. Mishra 2 1 M.Tech, Electronics and instrumentation Engineering, Shri G. S. Institute of Technology

More information

ENEE307 Lab 7 MOS Transistors 2: Small Signal Amplifiers and Digital Circuits

ENEE307 Lab 7 MOS Transistors 2: Small Signal Amplifiers and Digital Circuits ENEE307 Lab 7 MOS Transistors 2: Small Signal Amplifiers and Digital Circuits In this lab, we will be looking at ac signals with MOSFET circuits and digital electronics. The experiments will be performed

More information

Design cycle for MEMS

Design cycle for MEMS Design cycle for MEMS Design cycle for ICs IC Process Selection nmos CMOS BiCMOS ECL for logic for I/O and driver circuit for critical high speed parts of the system The Real Estate of a Wafer MOS Transistor

More information

VLSI Design. Static CMOS Logic

VLSI Design. Static CMOS Logic VLSI esign Static MOS Logic [dapted from Rabaey s igital Integrated ircuits, 2002, J. Rabaey et al.] EE4121 Static MOS Logic.1 ZLM Review: MOS Process at a Glance efine active areas Etch and fill trenches

More information

Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier

Chapter 5. Operational Amplifiers and Source Followers. 5.1 Operational Amplifier Chapter 5 Operational Amplifiers and Source Followers 5.1 Operational Amplifier In single ended operation the output is measured with respect to a fixed potential, usually ground, whereas in double-ended

More information

EEC 118 Lecture #12: Dynamic Logic

EEC 118 Lecture #12: Dynamic Logic EEC 118 Lecture #12: Dynamic Logic Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Outline Today: Alternative MOS Logic Styles Dynamic MOS Logic Circuits: Rabaey

More information

Digital Integrated CircuitDesign

Digital Integrated CircuitDesign Digital Integrated CircuitDesign Lecture 9 MOS Logic and Gate Circuits B B Y Wired OR dib brishamifar EE Department IUST Contents Introduction NMOS Logic Resistive Load Saturated Enhancement Load Linear

More information

ECE315 / ECE515 Lecture 8 Date:

ECE315 / ECE515 Lecture 8 Date: ECE35 / ECE55 Lecture 8 Date: 05.09.06 CS Amplifier with Constant Current Source Current Steering Circuits CS Stage Followed by CG Stage Cascode as Current Source Cascode as Amplifier ECE35 / ECE55 CS

More information

1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6)

1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6) CSE 493/593 Test 2 Fall 2011 Solution 1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6) Decreasing of W to make the gate slower,

More information

General Structure of MOS Inverter

General Structure of MOS Inverter General Structure of MOS Inverter Load V i Drive Department of Microelectronics and omputer Science, TUL Digital MOS ircuits Families Digital MOS ircuits PMOS NMOS MOS BiMOS Depletion mode load Enhancement

More information

ECE380 Digital Logic. Logic values as voltage levels

ECE380 Digital Logic. Logic values as voltage levels ECE380 Digital Logic Implementation Technology: NMOS and PMOS Transistors, CMOS logic gates Dr. D. J. Jackson Lecture 13-1 Logic values as voltage levels V ss is the minimum voltage that can exist in the

More information

BJT Amplifier. Superposition principle (linear amplifier)

BJT Amplifier. Superposition principle (linear amplifier) BJT Amplifier Two types analysis DC analysis Applied DC voltage source AC analysis Time varying signal source Superposition principle (linear amplifier) The response of a linear amplifier circuit excited

More information

Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1

Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Lecture 16 Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Outline Complementary metal oxide semiconductor (CMOS) Inverting circuit Properties Operating points Propagation delay Power dissipation

More information

Lecture 11 Circuits numériques (I) L'inverseur

Lecture 11 Circuits numériques (I) L'inverseur Lecture 11 Circuits numériques (I) L'inverseur Outline Introduction to digital circuits The inverter NMOS inverter with resistor pull-up 6.12 Spring 24 Lecture 11 1 1. Introduction to digital circuits:

More information

CHAPTER 3 PERFORMANCE OF A TWO INPUT NAND GATE USING SUBTHRESHOLD LEAKAGE CONTROL TECHNIQUES

CHAPTER 3 PERFORMANCE OF A TWO INPUT NAND GATE USING SUBTHRESHOLD LEAKAGE CONTROL TECHNIQUES CHAPTER 3 PERFORMANCE OF A TWO INPUT NAND GATE USING SUBTHRESHOLD LEAKAGE CONTROL TECHNIQUES 41 In this chapter, performance characteristics of a two input NAND gate using existing subthreshold leakage

More information

Designing Of A New Low Voltage CMOS Schmitt Trigger Circuit And Its Applications on Reduce Power Dissipation

Designing Of A New Low Voltage CMOS Schmitt Trigger Circuit And Its Applications on Reduce Power Dissipation IJISET - International Journal of Innovative Science, Engineering & Technology, Vol. Issue 1, December 015. www.ijiset.com ISSN 348 7968 Designing Of A New Low Voltage CMOS Schmitt Trigger Circuit And

More information

Low-Voltage Wide Linear Range Tunable Operational Transconductance Amplifier

Low-Voltage Wide Linear Range Tunable Operational Transconductance Amplifier Low-Voltage Wide Linear Range Tunable Operational Transconductance Amplifier A dissertation submitted in partial fulfillment of the requirement for the award of degree of Master of Technology in VLSI Design

More information

CMOS Schmitt Trigger A Uniquely Versatile Design Component

CMOS Schmitt Trigger A Uniquely Versatile Design Component CMOS Schmitt Trigger A Uniquely Versatile Design Component INTRODUCTION The Schmitt trigger has found many applications in numerous circuits, both analog and digital. The versatility of a TTL Schmitt is

More information

ECEN 474/704 Lab 6: Differential Pairs

ECEN 474/704 Lab 6: Differential Pairs ECEN 474/704 Lab 6: Differential Pairs Objective Design, simulate and layout various differential pairs used in different types of differential amplifiers such as operational transconductance amplifiers

More information

Today's Goals. Finish MOS transistor Finish NMOS logic Start CMOS logic

Today's Goals. Finish MOS transistor Finish NMOS logic Start CMOS logic Bi Today's Goals Finish MOS transistor Finish Start Bi MOS Capacitor Equations Threshold voltage Gate capacitance V T = ms Q i C i Q II C i Q d C i 2 F n-channel - - p-channel ± ± + + - - Contributions

More information

Metal-Oxide-Silicon (MOS) devices PMOS. n-type

Metal-Oxide-Silicon (MOS) devices PMOS. n-type Metal-Oxide-Silicon (MOS devices Principle of MOS Field Effect Transistor transistor operation Metal (poly gate on oxide between source and drain Source and drain implants of opposite type to substrate.

More information

Practice 6: CMOS Digital Logic

Practice 6: CMOS Digital Logic Practice 6: CMOS Digital Logic Digital Electronic Circuits Semester A 2012 The MOSFET as a Switch The MOSFET as a Switch We can look at the MOSFET as a Switch, passing the data between the diffusions when

More information

Reading. Lecture 17: MOS transistors digital. Context. Digital techniques:

Reading. Lecture 17: MOS transistors digital. Context. Digital techniques: Reading Lecture 17: MOS transistors digital Today we are going to look at the analog characteristics of simple digital devices, 5. 5.4 And following the midterm, we will cover PN diodes again in forward

More information

MTLE-6120: Advanced Electronic Properties of Materials. Semiconductor transistors for logic and memory. Reading: Kasap

MTLE-6120: Advanced Electronic Properties of Materials. Semiconductor transistors for logic and memory. Reading: Kasap MTLE-6120: Advanced Electronic Properties of Materials 1 Semiconductor transistors for logic and memory Reading: Kasap 6.6-6.8 Vacuum tube diodes 2 Thermionic emission from cathode Electrons collected

More information

4-bit counter circa bit counter circa 1990

4-bit counter circa bit counter circa 1990 Digital Logic 4-bit counter circa 1960 8-bit counter circa 1990 Logic gates Operates on logical values (TRUE = 1, FALSE = 0) NOT AND OR XOR 0-1 1-0 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1 0 1 0 1 1 1 1 1 0 0 0

More information

Analysis and Design of Analog Integrated Circuits Lecture 6. Current Mirrors

Analysis and Design of Analog Integrated Circuits Lecture 6. Current Mirrors Analysis and Design of Analog Integrated Circuits ecture 6 Current Mirrors Michael H. Perrott February 8, 2012 Copyright 2012 by Michael H. Perrott All rights reserved. From ecture 5: Basic Single-Stage

More information

Lecture Summary Module 1 Switching Algebra and CMOS Logic Gates

Lecture Summary Module 1 Switching Algebra and CMOS Logic Gates Lecture Summary Module 1 Switching Algebra and CMOS Logic Gates Learning Outcome: an ability to analyze and design CMOS logic gates Learning Objectives: 1-1. convert numbers from one base (radix) to another:

More information

Design and Implementation of Complex Multiplier Using Compressors

Design and Implementation of Complex Multiplier Using Compressors Design and Implementation of Complex Multiplier Using Compressors Abstract: In this paper, a low-power high speed Complex Multiplier using compressor circuit is proposed for fast digital arithmetic integrated

More information

IC Layout Design of 4-bit Universal Shift Register using Electric VLSI Design System

IC Layout Design of 4-bit Universal Shift Register using Electric VLSI Design System IC Layout Design of 4-bit Universal Shift Register using Electric VLSI Design System 1 Raj Kumar Mistri, 2 Rahul Ranjan, 1,2 Assistant Professor, RTC Institute of Technology, Anandi, Ranchi, Jharkhand,

More information

! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements

! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute.  From state elements ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential

More information

INTRODUCTION TO ELECTRONICS EHB 222E

INTRODUCTION TO ELECTRONICS EHB 222E INTRODUCTION TO ELECTRONICS EHB 222E MOS Field Effect Transistors (MOSFETS II) MOSFETS 1/ INTRODUCTION TO ELECTRONICS 1 MOSFETS Amplifiers Cut off when v GS < V t v DS decreases starting point A, once

More information

Power-Area trade-off for Different CMOS Design Technologies

Power-Area trade-off for Different CMOS Design Technologies Power-Area trade-off for Different CMOS Design Technologies Priyadarshini.V Department of ECE Sri Vishnu Engineering College for Women, Bhimavaram dpriya69@gmail.com Prof.G.R.L.V.N.Srinivasa Raju Head

More information

Microelectronics Exercises of Topic 5 ICT Systems Engineering EPSEM - UPC

Microelectronics Exercises of Topic 5 ICT Systems Engineering EPSEM - UPC Microelectronics Exercises of Topic 5 ICT Systems Engineering EPSEM - UPC F. Xavier Moncunill Autumn 2018 5 Analog integrated circuits Exercise 5.1 This problem aims to follow the steps in the design of

More information

ELEC 350L Electronics I Laboratory Fall 2012

ELEC 350L Electronics I Laboratory Fall 2012 ELEC 350L Electronics I Laboratory Fall 2012 Lab #9: NMOS and CMOS Inverter Circuits Introduction The inverter, or NOT gate, is the fundamental building block of most digital devices. The circuits used

More information

Near-threshold Computing of Single-rail MOS Current Mode Logic Circuits

Near-threshold Computing of Single-rail MOS Current Mode Logic Circuits Research Journal of Applied Sciences, Engineering and Technology 5(10): 2991-2996, 2013 ISSN: 2040-7459; e-issn: 2040-7467 Maxwell Scientific Organization, 2013 Submitted: September 16, 2012 Accepted:

More information

Microelectronics Circuit Analysis and Design

Microelectronics Circuit Analysis and Design Neamen Microelectronics Chapter 4-1 Microelectronics Circuit Analysis and Design Donald A. Neamen Chapter 4 Basic FET Amplifiers Neamen Microelectronics Chapter 4-2 In this chapter, we will: Investigate

More information

Operational Amplifiers Part I of VI What Does Rail-to-Rail Input Really Mean? by Bonnie C. Baker Microchip Technology, Inc.

Operational Amplifiers Part I of VI What Does Rail-to-Rail Input Really Mean? by Bonnie C. Baker Microchip Technology, Inc. Operational Amplifiers Part I of VI What Does Rail-to-Rail Input Really Mean? by Bonnie C. Baker Microchip Technology, Inc. bonnie.baker@microchip.com Some single-supply operational amplifier advertisements

More information

B.E. SEMESTER III (ELECTRICAL) SUBJECT CODE: X30902 Subject Name: Analog & Digital Electronics

B.E. SEMESTER III (ELECTRICAL) SUBJECT CODE: X30902 Subject Name: Analog & Digital Electronics B.E. SEMESTER III (ELECTRICAL) SUBJECT CODE: X30902 Subject Name: Analog & Digital Electronics Sr. No. Date TITLE To From Marks Sign 1 To verify the application of op-amp as an Inverting Amplifier 2 To

More information

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo

Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Combinational vs. Sequential Logic In Combinational Logic Circuit Out In Combinational Logic Circuit

More information

EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies. Overview of Physical Implementations

EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies. Overview of Physical Implementations EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies Mar 12, 2013 John Wawrzynek Spring 2013 EECS150 - Lec15-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)

More information

EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies

EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies Feb 14, 2012 John Wawrzynek Spring 2012 EECS150 - Lec09-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)

More information