ECE 471/571 Combinatorial Circuits Lecture-7. Gurjeet Singh

Transcription

1 ECE 471/571 Combinatorial Circuits Lecture-7 Gurjeet Singh

2 Propagation Delay of CMOS Gates

3 Propagation delay of Four input NAND Gate

4 Disadvantages of Complementary CMOS Design Increase in complexity Larger implementation area Propagation delay deteriorates rapidly as a function of fan-in

5 Disadvantages of Complementary CMOS Design Large number of transistors increases overall capacitance of the gate Series connection causes slowdown

6 Design Techniques for Large Fan-in

7 Transistor Sizing Increase the size of transistor But increasing the transistor size also increases propagation delay

8 Progressive Transistor Sizing

9 Input Reordering

10 Logic Restructuring

11 Optimizing Performance in Combinatorial Networks tp0 = intrinsic delay of an inverter f = effective fan-out(ratio between external load and input capacitance), also called electrical effort p = ratio of intrinsic delays of the complex gates and the simple inverter. Function of gate topology as well as layout style g = logical effort

12 Estimated of p and g

13 Optimizing Performance in Combinatorial Networks gate effort h = fg

14 Optimizing Performance in Combinatorial Networks Total delay of path through combinatorial logic block Find minimum delay by finding N-1 partial derivative and set them to zero, we get Path logical effort, G can be found by multiplying logical efforts of all the gates G= gi

15 Optimizing Performance in Combinatorial Networks Path effective fan-out(or electrical effort) F, F= CL/Cg1 Some of the drive current is directed along path while some is directed of the path. We need to calculation branching effort as well b= (Con-path+Coff-path)/Con-path Path Branching effort can be calculated by B= bi

16 Optimizing Performance in Combinatorial Networks Path Electrical effort can be calculated from electrical and branching effort F = ℿ(fi/bi) = (ℿfi)/B Total path effort H can be defined as H = ℿhi = ℿgifi = GFB Gate effort that minimizes the path delay is Minimum delay of path is given by:

17 Optimizing Performance in Combinatorial Networks If s1 is the sizing factor of first gate in the chain g2s2cref = (f1/b1)g1s1cref For gate i in the chain, this yields si = (g1s1/gi)ℿi-1j=1(fj/gj)

18 Example F G B H h f1 f2 f3 f4 a b c = CL/Cg1 = 5 = 1*(5/3)*(5/3)*1 = 1 (no branching) = GFB = 4 (125/9) = 1.93 = 1.93*(3/5) = 1.16 = 1.93 = f1g1/g2 = f1f2g1/g3 = f1f2f3g1/g4 = 25/9 = 125/9 = 1.93 =1.16 =1.16 =1.34 =2.60

19 Power Consumption in CMOS Logic Gates Dynamic power dissipation, is switching activity Static component based on topology Dynamic component based on timing behaviour(glitching) 0->1 po is probability when output is zero p1 is probability when output is one

20 Example

21 Signal Statistics Let, pa and pb be the probabilities that the inputs A and B are one.assume inputs are not correlated. The probability the the output node is 1 is given by Probability of transition from 0 to 1 is

22 Intersignal Correlations

23 Dynamic or Glitching Transitions

24 Design Techniques to Reduce Switching Activity

25 Logic Restructuring

26 Input ordering

27 Time-multiplexing Resources

28 Glitch Reduction by balancing signal paths

29 Ratioed Logic

30 Features Lesser number of transistors compared to Complementary approach(n+1 compared to 2N) Nominal High Voltage VOH is VDD Nominal low voltage is not 0V Reduced Noise Margin Increase in static power dissipation.

31 Pseudo NMOS Inverter

32 NAND vs NOR in Pseudo-NMOS Which one would you prefer to implement in pseudo-nmos?

33 Building Better Loads Differential Logic Requires each input is provided by complementary format Positive Feedback Ensure that load device is turned off when not needed One example is Differential Cascode Voltage Switch Logic(DCVSL)

34 Single-Ended vs Differential Differential reduces number of transistors required by 2 Differential removes need for inverter stage Differential need more wires for interconnects High Dynamic power dissipation

35 Pass-Transistor Logic Advantages Fewer transistors required Disadvantages NMOS is poor in pulling a node to VDD NMOS experience body effect when pulling voltage to high

36 Voltage Swing for Pass Transistor Circuits

37 Energy of Pass-Transistor Logic

38 Differential Pass-Transistor Logic (CPL or DPL)

39 Properties of DPL Both input and output signal and its complement available. Output either connected to VDD or GND via low-resistance path Since design is almost similar. It makes it easier for modular design library

40 Robust and Efficient Pass-Transistor Design

41 Level Restoration

42 Level Restoration

43 Multiple Threshold Transistors

44 Transmission Gate Logic