EXPERIMENT 4 CMOS Inverter and Logic Gates

Transcription

1 İzmir University of Economics EEE 332 Digital Electronics Lab A. Background EXPERIMENT 4 CMOS Inverter and Logic Gates CMOS (Complementary MOS) technology uses tarnsistors together with transistors to implement logic functions. The average static power dissipation is almost zero, since no current flows through. A CMOS inverter is given in Fig Substrate of is connected to, whereas the substrate of is grounded. A.1. Voltage transfer Characteristics Fig CMOS Inverter The voltage transfer characteristics (VTC) of the above inverter may be obtained by varying input voltage from 0 to. A typical Voltage Transfer Characteristics (VTC) is given on Fig H t + V TP : OFF : NONSAT slope = -1 : SAT : NONSAT : SAT : SAT Fig Voltage Transfer Characteristics (VTC) of an CMOS Inverter t - V TN L 0 VIL VIt : NONSAT : SAT VIH slope = -1 - V TP : NONSAT : OFF VDD 4-1

2 For the given value of the input voltage, then V GSN = and V SGP = -, and the states of and are determined accordingly. The states of the transistors are indicated on the VTC given on Fig The input low voltage (logic 0) ranges from 0 to L. The corresponding output high range (logic 1) is from H to. For the input high (logic 1) range from H to, output low voltages range from L to 0. At the transition point t, both transistors are SAT. Using the SAT region equations of the transistors and I =K (V V ) I =K (V V ) and using the fact that I DSN = I SDP, the threshold voltage t is obtained as, V = V V + K K V 1+ K K When V TN = - V TP, and K N = K P, symmetric VTC is obtained with t = / 2. For the symmectric VTC, the low and high voltage ranges are obtained as: and V =V + (V V V ); V =V + (V V V ) V =V V ; V =V + V The noise margins are obtained as NM L = L L NM H = H H A.2. Average Power Dissipation The average power dissipated in the gate is calculated assuming half of the period, input is high (output is low) and during the other half input is low (output is high). When the output is high (i.e., = 0 ), the current drawn from the source is zero, I DD(OH) = 0, since the is OFF ( is in NONSAT). For = 5 V, then = 0, the no current is drawn from, i.e. I DD(OL) = 0, since is OFF (and is in NONSAT). Then the average power is therefore I () = I () I () 2 =0 4-2

3 A.3. Logic Gates A CMOS logic gate is composed of two blocks; an N-Block and a P-Block as shown in Fig The substrates of taransistors are connected to and the substrates of transistors are connected to ground. A B.. A B.. Block Block Y Fig General Structure of CMOS Gates The structure of block is exactly the same as in logic. The block has a complemented structure compared to block. Consider the NOR gate given in Fig Y A M 1 M 2 B Fig CMOS NOR Gate The truth table and the states of the transistors corresponding to these inputs are summarized in Table 4.1. Logic 0 is represented by 0 V, and Logic 1 is represented by. Table 4.1. CMOS NOR Gate Operation A B M 1 M 2 Y 0 0 OFF OFF NONSAT NONSAT OFF NONSAT NONSAT (OFF) OFF NONSAT OFF OFF NONSAT NONSAT NONSAT OFF OFF 0 4-3

4 As seen from the figure, block is exactly the same as in implementation, however block consists of series transistors as complementary structure to parallel transistors in Block. A CMOS NAND gate is given in Fig M 2 M 1 Fig CMOS NAND Gate The truth table and the states of the transistors corresponding to these inputs are summarized in Table 4.1. Logic 0 is represented by 0 V, and Logic 1 is represented by. Table 4.2. CMOS NAND Gate Operation A B M 1 M 2 Y 0 0 OFF OFF NONSAT NONSAT OFF NONSAT (OFF) NONSAT OFF NONSAT OFF OFF NONSAT NONSAT NONSAT OFF OFF 0 As seen from above figure, block in NAND gate is exactly the same as in implementation, however block consists of parallel transistors as complementary structure to series transistors in Block. 4-4

5 B. Preliminary Work B.1. Inverter Characteristics Consider the CMOS inverter given in Fig The transistor parameters are given on the right. i. Determine and plot the voltage transfer characteristics (VTC) vs on Fig ii. Determine the critical voltages input voltages L and H, and the output voltages L and H. iii. Determine low noise margin (NM L) and high noise margin (NM H) values. = 5 V Transistor Parameters V Tn = 1.4 V K n = 0.45 ma/v 2 Fig CMOS Inverter, volts Input voltages L = H = Output voltages L= H= Noise Margins NM L = NM H = , volts Fig Voltage Transfer Characteristics of the CMOS Inverter 4-5

6 B.2. CMOS Gate Connections i. Implement the CMOS inverter given in Fig. 4.8 using the TC4007UBP integrated circuit package. Indicate the terminal numbers on the NOR Gate. (You are expected to suggest 3 connections) = 5 V = 5 V = 5 V Fig CMOS Inverter Implementations Using TC4007UBP Integrated Circuit 4-6

7 ii. Implement the NOR gate given in Fig. 4.9 using the TC4007UBP integrated circuit package. Indicate the terminal numbers on the NOR Gate. Y A M 1 M 2 B Fig NOR Gate Implementation of the CMOS NOR Gate Using TC4007UBP Integrated Circuit iii. Implement the NAND gate given in Fig. 4.9 using the TC4007UBP integrated circuit package. Indicate the terminal numbers on the NOR Gate. M 2 M 1 Fig NOR Gate Implementation of the CMOS NOR Gate Using TC4007UBP Integrated Circuit 1. Implement the following logic function using technology. " =# &&&&&&&&&&&&&& ( $+% ) 4-7

8 C. Experimental Work C.1. CMOS Interter Voltage Transfer Characteristics i. Set up the inverter the you have suggested in the Preliminary Work Using TC4007UBP Integrated Circuit package. = 5 V Fig CMOS Inverter Implementations Using TC4007UBP Integrated Circuit (a) Obtain and plot vs on Fig (Get more measurements around L and H. VI VO, volts Input voltages L = H = Output voltages L= H= Noise Margins NM L = NM H = Fig VTC of CMOS Inverter, volts 4-8

9 (b) Measure the current drawn from the power suppy for = 0 and = 5 V. Complete the values in Table 4.3. Calculate the total power drawn from the source. Table 4.3 I DD (ma) Parameter P T 0 DD(OH) 5 DD(OL) C.2. CMOS NOR and NAND Gates (a) Set up the NOR gate you have constructed in Fig. 4.8 using the TC4007UBP integrated circuit package. Do the measurements to fill in the Voltage Truth Table given below. Y A M 1 M 2 B Fig NOR Gate Implementation of the CMOS NOR Gate Using TC4007UBP Integrated Circuit (b) Set up the NAND gate you have implemented using the TC4007UBP integrated circuit package. Indicate the terminal numbers on the NOR Gate. Do the measurements to fill in the Voltage Truth Table given below. 4-9

10 M 2 M 1 Fig NOR Gate Implementation of the CMOS NOR Gate Using TC4007UBP Integrated Circuit Set up the implementation of the logic function Y =A &&&&&&&&&&&&&& ( B+C ) you have designed in Preliminary Work. Do the measurements and complete the Voltage Truth Table given below