Digital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
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1 Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC
2 Ratioed Logic Introduction Digital IC EE141 2
3 Ratioed Logic design Basic concept Resistive load Depletion NMOS Pseudo NMOS DCVSL logic Pseudo NMOS logic effort Digital IC 3
4 Ratioed Logic design Basic concept Resistive load Depletion NMOS Pseudo NMOS DCVSL logic Pseudo NMOS logic effort Digital IC 4
5 Ratioed Logic V DD V DD V DD Resistive Load R L Depletion Load V T < 0 PMOS Load F F V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudo-nmos Goal: to reduce the number of devices over complementary CMOS Goal: to reduce the number of devices over complementary CMOS Digital IC 5
6 How to obtain a good load a good load Low power V OL tend to zero Charge time short (large charge current) Memory address decoder match the structure Low power when address hold the line Change quickly when address content changed Digital IC 6
7 Ratioed Logic design Basic concept Resistive load Depletion NMOS Pseudo NMOS DCVSL logic Pseudo NMOS logic effort Digital IC 7
8 Ratioed Logic-resistive load V DD N transistor + Load Resistive Load R L V OH =V DD In 1 In 2 In 3 PDN F V OL = RPN R PN +R L ssymetrical response Static power consumption V SS t pl =0.69 R L C L Digital IC 8
9 Resistive load R L not be to low V OL R R PDN PDN R L V DD For wide range low noise margin,r L >>R PDN R L not be to high enough large current could give quick switch time, because t plh 0.69RLC L t 0.69( R R ) C phl PDN Decrease power consumption SP L L Digital IC 9
10 Ratioed Logic design Basic concept Resistive load Depletion NMOS Pseudo NMOS DCVSL logic Pseudo NMOS logic effort Digital IC 10
11 ctive Loads V DD V DD Depletion Load V T < 0 PMOS Load F V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS depletion load NMOS pseudo-nmos Depletion load has negative threshold voltage Digital IC 11
12 Depletion nmos load assume the load tran.works at saturate state, just like a current source I L Practically, the load curve slant down k n, load 2 Load transistor s source is connect with output, which V SB will effect threshold voltage Compared with resistive load, depletion load has smaller area 40k resistive load need 3200m 2 (0.5um) which could occupy 1000 unit transistor V Tn 2 Digital IC 12
13 Depletion NMOS ratios computing t least, V OL should close next stage MOS transistor: V R R W out PDN R V PDN NMOSload NMOSsload W t PDN Inverter: nmos Vdd R R 0.3V PDN NMOSsload dd 0.3V dd Digital IC 13
14 Ratioed Logic design Basic concept Resistive load Depletion NMOS Pseudo NMOS DCVSL logic Pseudo NMOS logic effort Digital IC 14
15 Pseudo-NMOS ratios PMOS s source and substrate voltage is always zero,no body effect Load transistor s saturate current is I L k p 2 ( V DD V Tp 2 ) pmos load current is larger than that of nmos Digital IC 15
16 Pseudo-NMOS ratios computing k n (( V DD V Tn ) V OL 2 V 2 OL ) k p (( V DD V Tp ) V DST p V 2 DST 2 p ) 0 V OL W W p n k p μ ( V n k DD n ( V V DD Tp ) V V Tn DST ) 2 = 3800cm /v.s,μ VOLn V p DSTp p p W p W n p n V DSTp 2 = 1800cm /v.s pmos load for 1/5, always 1/3-1/6 Digital IC 16
17 Pseudo NMOS logic design rule Static power Constrains should be regarded P average V I L should be lower in order to decrease power V OL =I L R PDN should be lower in order to obtain effective low voltage I L should high in order to decrease t plh =(C L V dd )/(2I L ) R PDN should be small in order to decrease t phl =0.69R PDN C L, dd I low k p 2 V ( V Digital IC 17 dd dd V Pull-down transistors should be wider, not benefit from both power and delay T 2 )
18 V ou t [V] Pseudo-NMOS VTC W/L p = W/L p = W/L p = 0.5 W/L p = 0.25 W/L p = V in [V] Digital IC 18
19 Load curve analysis Resistive load I L V DD V R More output voltage, lower charge current, more time Ideally, constant current source Charge current does not be decreased by output voltage L out Digital IC 19
20 Pseudo-NMOS ratioed logic Pseudo-NMOS ratioed logic merits N-fan-in needs N+1 transistors,with smaller area and parasitic cap. Every input only connects with one transistor, which load cap. is smaller as front stage logic. shortcoming Static power,1mw per logic,50w consumption if chip has 100,000 such logic structure! application Not fit for large scale circuit Only apply on high speed circuit Only apply on 1-state on most output(etc. decoder) Large fan-in Digital IC 20
21 Improved Loads V DD Enable M1 M2 M1 >> M2 F B C D C L daptive Load Digital IC 21
22 Improved Loads (2) V DD V DD M1 M2 Out Out B B PDN1 PDN2 V SS V SS Differential Cascode Voltage Switch Logic (DCVSL) Digital IC 22
23 Ratioed Logic design Basic concept Resistive load Depletion NMOS Pseudo NMOS DCVSL logic Pseudo NMOS logic effort Digital IC 23
24 V oltage [V] DCVSL Example Out 2.5 B Out B B B ,B,B B B XOR-NXOR gate Time [ns] Digital IC 24
25 Pseudo-nMOS Power Pseudo-nMOS draws power whenever Y = 0 Called static power P = I V DD few m / gate * 1M gates would be a problem This is why nmos went extinct! Use pseudo-nmos sparingly for wide NORs Turn off pmos when not in use en B C Y Digital IC 25
26 Pass-Transistor Logic Introduction Digital IC 26 EE141
27 Pass- transistor logic outline Pass-transistor principle Pass-transistor VTC How to solve pass-transistor threshold drop issue Transmission gate principle Some issues of transmission gate Digital IC 27
28 Pass-Transistor Logic B Inputs Switch Network Out B B Out N transistors No static consumption Pass-transistor logic is a path, not a road connected with rail directly! Digital IC 28
29 Example: ND Gate B B F = B 0 Digital IC 29
30 Pass Transistors Transistors can be used as switches g s d g s d 1: Circuits & Layout Digital IC Slide 30
31 Pass Transistors Transistors can be used as switches s g d s s g = 0 g = 1 d d Input g = 1 Output 0 strong 0 g = 1 1 degraded 1 s g d s s g = 0 g = 1 d d Input g = 0 Output 0 degraded 0 g = 0 strong 1 Digital IC Slide 31
32 Voltage [V] NMOS-Only Logic In V DD x 1.5m/0.25m 0.5m/0.25m 0.5m/0.25m Out 3.0 In NMOS keep on,then 2.0 Out x V GS >V t 1.0 V DG =0,which means NMOS always works in Time [ns] the saturation state Digital IC 32
33 NMOS-only Switch C = 2.5 V C = 2.5 V = 2.5 V = 2.5 V B M 2 B M n C L M 1 V B does not pull up to 2.5V, but 2.5V V TN Threshold voltage loss causes static power consumption NMOS has higher threshold (body effect) Digital IC 33
34 The proper way of cascading pass gates Weak for passing high voltage V min V V, V s G T D Proper way of cascading pass transistors,which will not accumulate threshold drop Digital IC 34
35 Output of passing-transistor should not be connected with the gate of next stage Digital IC 35
36 Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well Digital IC Slide 36
37 Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well a g gb b g = 0, gb = 1 a b g = 1, gb = 0 a b Input Output g = 1, gb = 0 0 strong 0 g = 1, gb = 0 1 strong 1 a g b a g b a g b gb gb gb Digital IC Slide 37
38 Tristates Tristate buffer produces Z when not enabled EN Y EN 0 0 Y EN Y EN Digital IC Slide 38
39 Tristates Tristate buffer produces Z when not enabled EN Y EN 0 0 Z Y 0 1 Z EN Y EN Digital IC Slide 39
40 Nonrestoring Tristate Transmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on is passed on to Y EN Y EN Digital IC Slide 40
41 Tristate Inverter Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output EN EN Y Digital IC Slide 41
42 Tristate Inverter Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output EN EN Y Y Y EN = 0 Y = 'Z' EN = 1 Y = Digital IC Slide 42
43 Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 Y S 0 X 0 0 X X D0 D1 0 1 Y 1 1 X Digital IC Slide 43
44 Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 Y S 0 X X X 0 D0 D1 0 1 Y 1 1 X 1 Digital IC Slide 44
45 Gate-Level Mux Design Y SD SD 1 0 (too many transistors) How many transistors are needed? Digital IC Slide 45
46 Gate-Level Mux Design Y SD SD 1 0 (too many transistors) How many transistors are needed? 20 D1 S D0 Y D1 S D Y Digital IC Slide 46
47 Transmission Gate Mux Nonrestoring mux uses two transmission gates Digital IC Slide 47
48 Transmission Gate Mux Nonrestoring mux uses two transmission gates Only 4 transistors S D0 S Y D1 S Digital IC Slide 48
49 Inverting Mux Inverting multiplexer Use compound OI22 Or pair of tristate inverters Essentially the same thing Noninverting multiplexer adds an inverter D0 S S S D1 S Y D0 S S D1 S S Y D0 D1 0 1 S Y Digital IC Slide 49
50 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects 1: Circuits & Layout Digital IC Slide 50
51 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes Or four tristates S1S0 S1S0 S1S0 S1S0 D0 S0 S1 D0 D1 D Y D1 D2 Y D3 1 D3 Digital IC Slide 51
52 Pass- transistor logic outline Pass-transistor principle Pass-transistor VTC How to solve pass-transistor threshold drop issue Transmission gate principle Some issues of transmission gate Digital IC 52
53 Pass-transistor s VTC Digital IC 53
54 Complementary Pass Transistor Logic B B Pass-Transistor Network F (a) B B Inverse Pass-Transistor Network F B B B B B B B F=B B F=+B F=Ý (b) B F=B B F=+B F=Ý ND/NND OR/NOR EXOR/NEXOR Digital IC 54
55 Pass- transistor logic outline Pass-transistor principle Pass-transistor VTC How to solve pass-transistor threshold drop issue Solution 1:Level Restoring Transistor Resistive issue Digital IC 55
56 Solution 1:Level Restoring Transistor Level Restorer V DD V DD B M r M 2 M n X Out M 1 dvantage: Full Swing Restorer adds capacitance, takes away pull down current at X Ratio problem Digital IC 56
57 Voltage [V] Restorer Sizing W/L r =1.75/0.25 W/L r =1.50/ W/L r =1.0/0.25 W/L r =1.25/ Time [ps] Upper limit on restorer size Pass-transistor pull-down can have several transistors in stack Digital IC 57
58 pass- transistor logic outline Pass-transistor principle Pass-transistor VTC How to solve pass-transistor threshold drop issue Solution 1:Level Restoring Transistor Resistive issue Solution 2: Single Transistor Pass Gate with V T =0 Digital IC 58
59 Solution 2: Single Transistor Pass Gate with V T =0 V DD 0V 2.5V V DD V DD 0V Out 2.5V WTCH OUT FOR LEKGE CURRENTS Digital IC 59
60 pass- transistor logic outline Pass-transistor principle Pass-transistor VTC How to solve pass-transistor threshold drop issue Solution 3: Transmission Gate Complementary Pass-Transistor Logic Transmission gate principle Some issues of transmission gate Digital IC 60
61 Solution 3: Transmission Gate C C B B C C C = 2.5 V = 2.5 V B C L C = 0 V Digital IC 61
62 pass- transistor logic outline Pass-transistor principle Pass-transistor VTC How to solve pass-transistor threshold drop issue Transmission gate principle Some issues of transmission gate Digital IC 62
63 Pass-Transistor Based Multiplexer S VDD V DD S S M2 S F M1 B S GND In 1 S S In 2 Digital IC 63
64 Transmission Gate XOR B M2 B M1 B F B M3/M4 Digital IC 64
65 Transmission Gate Full dder P V DD V DD P C i C i P S Sum Generation V DD B P B P P V DD C o Carry Generation C i C i Setup C i P Similar delays for sum and carry Digital IC 65
66 pass- transistor logic outline Pass-transistor principle Pass-transistor VTC How to solve pass-transistor threshold drop issue Transmission gate principle Some issues of transmission gate Resistive issue Delay issue Digital IC 66
67 More detail about a processing of low-to-high Two transistors stories NMOS, For V GS =V DS, V GD =0<V t,then NMOS always works in the saturation or off state PMOS, For V GS =-2.5V, transistor turn from saturation to linear state More detail V V V out tp dd V V V tn tp out : V V NMOS out dd : V and tn : PMOS are in saturation NMOS in satur. PMOS in linear NMOS cut off PMOS in linear Digital IC 67
68 Transmission gate effective resistance of low-to-high Relatively constant R eq =R p R n R n k V n ( V DD DD V I Dn V V DD out V V out k out ' n Tn W ( ) L ) V N DSTn (( V DD V V DD out V V out Tn ) V DSTn V 2 2 DSTn ) R p V k p out 1 ( V V I DD Dp DD V Tp ) k ' p W ( ) L P (( V DD V V Tp DD )( V V out out V DD ( V ) out V 2 DD ) 2 ) Digital IC 68
69 pass- transistor logic outline Pass-transistor principle Pass-transistor VTC How to solve pass-transistor threshold drop issue Transmission gate principle Some issues of transmission gate Resistive issue Delay issue Complementary Pass-Transistor Logic Digital IC 69
70 Delay in Transmission Gate Networks Many applications use transmission like that Replaced by their equivalent resistances Digital IC 70
71 Digital IC How to do Solving the differential equation It is too complex to find precise solution,we have to find some approximate solution 71 Computing delay time )) ( ( i i i i eq i V V V V C R t V ) ( 1,, 1 1 i i i C i i C I I C t V dt CdV dt dq I I I I
72 Delay time is τ ( V close solution n ) CR k0 Break chain and Insert buffer n eq k CR eq n( n 1) 2 Digital IC 72
73 Transmission gate delay optimization Total delay time ssume all has n transmission gate,break chain every m switchs,buffer delay time is t buf t p 0.69[ 0.69CR n m eq m( m 1) CReq ] ( 2 n( m 1) n ( 1) t 2 m n m buf 1) t buf Digital IC 73
74 Optimal number of switch m optimal m optimal t p m t p 0 m n ntbuf 0.69CReq 2 2 m tbuf CR eq It is independent with n 0 Digital IC 74
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