MOS Logic and Gate Circuits. Wired OR

Transcription

1 MOS Logic and Gate Circuits A A A B A AB Y Wired OR

2 Contents Introduction NMOS Logic Resistive Load Saturated Enhancement Load Linear Enhancement Load Depletion Load Some Gates Transient in NMOS Circuit Pseudo-NMOS CMOS Logic Static CMOS Logic Gates NOT NAND NOR Realization of More Complicated Gate Circuits Transmission Gates Family NMOS Only Switch CMOS Differential Cascode Voltage Switch Logic Rules of Thumb Summary

3 Introduction The MOS inverter is the basic circuit exhibits all of the essential features of MOS Logic. Extension of MOS inverter concepts to NOR and NAND Gate is very simple. In this lecture we will analysis for VTC, NM, PD,. Both NMOS and CMOS circuits are considered. Digital MOS circuits can be classified into two categories: Static Circuits: require no clock or other periodic signal for operation. Clocks are required for static circuit in sequential logic Dynamic Circuits: require periodic clock signals, synchronized with data signals, for proper operation even in combinational logic

4 NMOS Logic Resistive Load W VoL C Speed L P RL Area Vo Vdd Vi +Vdd RL Vo V OL o Vi

5 NMOS Logic Resistive Load Properties N transistors + Load V OH = Vdd V OL = Vdd ( rn/(rn + RL)) Assymetrical response Static power consumption t PL = 0.69RLCL

6 NMOS Logic Saturated Enhancement Load Vds2 = Vgs2 + Vdd + Vdd Vds2 > Vgs2 V Vo V OH δvo δvi = 1 T2 M2 is in saturation Vi M2 M1 Vo β R V OL o V IL Vi V IH

7 NMOS Logic Saturated Enhancement Load V IL V V M1, M2 are in saturation IL T1 K(Vgs1 V ) = K(Vgs2 V ),V Cte T1 2 T2 δvo Vgs1 = Vi, Vgs2 = Vdd Vo = βr, β R > 1 δvi δvo 1 VI L VT 1 δvi T2 Vo V OH V OL o δvo δvi V IL V IH = 1 β R Vi

8 NMOS Logic Saturated Enhancement Load V OL V OL is difficult to obtain because it is the output voltage when input equal to V OH, the resulting expression is a fourth order polynomial! Vo V OH δvo δvi = 1 β R V OL o V IL Vi V IH

9 NMOS Logic Saturated Enhancement Load V IH M1 is in triode and M2 in saturation δvo δi1 = δvi δvi δvo rds1 rds2 rds1 = δ i ( rds1 rds2) ( ) 1 i2 = K 2(Vgs2 V T2) 2 δi KVo 1 δvi 2 i1 = K1 Vgs1 VT1 Vo Vo 2 1 = 1 2 δi δvo K ( Vgs1 V Vo) δvo KVo δvi K (Vgs1 V Vo) 1 = 1 T1 1 = = Vo = Vi V 2 V 1 T1 T1 V IH T1 Vi = VIH = Vo 2 1

10 NMOS Logic Saturated Enhancement Load V IH M1 is in triode and M2 in saturation i = i K ( V V ) Vo Vo 2 = K (Vdd Vo V ) 2 2(Vdd V ) VT1 3β IH T1 2 T2 T2 VIH = + R

11 NMOS Logic Saturated Enhancement Load NM NML = V V Some tenth of volt IL OL NMH = V V = Vdd V V OH IH T2 IH Power P 0, P = I Vdd dish disl d P = 1 2I Vdd dis d

12 NMOS Logic Linear Enhancement Load VGG Vdd + V T2 M2 is in triode Linear Enhancement Load VGG Vi +Vdd M2 Vo M1

13 NMOS Logic Linear Enhancement Load VTC By this circuit the V OH can be increased (or Vdd can be decreased because Vo max = Vdd ) Vo Vdd V OL o V IL Vdd Vi V T V IH

14 NMOS Logic Linear Enhancement Load V IL M1 is in saturation and M2 in triode δvo δi1 δi1 δvds2 = rds2 = δvi δvi δvi δi ( ) δi2 = K2( VGG Vo VT2 δvds2 Vds2) 2 i2 = K2 Vgs2 VT2 Vds2 Vds i1 = K 1(Vi V T1) 2 δi1 = K1( Vi VT1) δvi δvo K(Vi 1 V T1) = 1 = δvi K (VGG Vo V Vds2) V = f(vo) IL 2 T2 V IH M1 and M2 are in triode rds2 rds1 rds2

15 NMOS Logic Linear Enhancement Load Disadvantages: More chip area is required (since an extra voltage source VGG) Additional interconnection on the chip is needed β R The required value of is even larger than a saturated load +Vdd VGG M2 Vo Vi M1

16 NMOS Logic Depletion Load Ion implantation processing step is needed to create depletion device, but overcome the disadvantages of the previous circuit +Vdd M2 Vo Vi M1

17 NMOS Logic Depletion Load VTC Vi = Low i = 0, M1 in cutoff i = i = K2 2 if M2 is in saturation then i 2 = (Vgs2 V T2),Vgs2 = 0 i2 > 0 2 Therefore M2 is in triode Vo Vdd V OL o V IL V T V IH Vdd Vi

18 NMOS Logic Depletion Load V OL, V IL, V IH 2 K2 2 K 1 ( VOH VT1) VOL VOL 2 = (0 V T2) V OL =? 2 δvo K(Vgs1 V ) = = = = δvi K (Vgs2 V Vds2) 1 T1 1 1, i1 i2 V IL? 2 T2 2 K2 2 δvo i1 = K 1 ( VIH VT1) Vds1 Vds1 2 = i 2 = (0 V T2), = 1 V IH =? 2 δvi

19 NMOS Logic Some Gates In all previous structures which different only in load, the following Gates can be implemented. Note that the NMOS Gates are not available as separately packaged individual circuits, but they are used extensively in LSI systems NOR Gates NAND Gates

20 NMOS Logic Some Gates NOR Gate +Vdd A M1 B RL M2 Y A B Y

21 NMOS Logic Some Gates NAND Gate +Vdd A RL M2 Y A B Y B M1

22 NMOS Logic Some Gates In NOR Gate two transistors are paralleled but in NAND Gate two transistors are in series. Because of the need for increased area when adding NAND inputs, NAND logic with more than 2 inputs is not economically be attractive in NMOS. NOR logic is preferable In NAND the M2 has body effect In NOR we need the less interconnection (this can be shown from layout)

23 NMOS Logic Transient in NMOS Circuits Saturated Enhancement Load +Vdd M2 Cgs2 Cgd1 +Vdd Cs sub2 CL Vo Vi M1 Cd sub1 C = C + Ceq + Ceq + Cgs2 + 2 Cgd1 tot L d sub1 s sub2

24 NMOS Logic Super Buffer (1) If Fan-out is very large then C tot will be large. For reduction it and decrease the switching time the Super Buffer circuit is used In this circuit if Vi is Low state then V1 will be high very more rapid than Vo. Thus the Gate of M2 is in high state very rapidly. Therefore M2 will be in saturation which result the reduction of switching time (t on ) +Vdd +Vdd M4 M2 V1 Vo M1 M3 Vi Super Buffer (1) Circuit

25 NMOS Logic Super Buffer (2) It is non-inverting Describe the operation of this circuit! M4 +Vdd +Vdd M2 Vi V1 M1 M3 Vo Super Buffer (2) Circuit

26 NMOS Logic Pseudo-NMOS What makes a circuit fast? I = C dv/dt -> tpd (C/I) DV low capacitance high current small swing Logical effort is proportional to C/I PMOS are the enemy! High capacitance for a given current Can we take the PMOS capacitance off the input? Various circuit families try to do this

27 NMOS Logic Pseudo-NMOS In the old days, NMOS processes had no PMOS Instead, use pull-up transistor that is always ON In CMOS, use a PMOS that is always ON Make PMOS about ¼ effective strength of pulldown network

28 NMOS Logic Pseudo-NMOS Uses a p-type as a resistive pullup, n-type network for pulldowns +Vdd M2 Vo Vi M1

29 NMOS Logic Pseudo-NMOS Characteristics Compared to CMOS, this family has higher packing density, since for n inputs only n+1 transistors are required The main disadvantages with Pseudo-NMOS Gates is the large static power dissipation that occurs whenever a pulldown path is activated Has much smaller pullup network than static gate Pulldown time is longer because pullup is fighting Vi +Vdd M2 Vo M1

30 NMOS Logic Pseudo-NMOS Output Voltages Logic 1 output is always at Vdd Logic 0 output is above Vss V OL = 0.25 (Vdd - Vss) is one plausible choice +Vdd M2 Vo Vi M1

31 NMOS Logic Pseudo-NMOS Design Topics For logic 0 output, pullup and pulldown form a voltage divider Must choose n, p transistor sizes to create effective resistances of the required ratio Effective resistance of pulldown network must be computed in worst case series n-types means larger transistors Vi +Vdd M2 Vo M1

32 NMOS Logic Pseudo-NMOS Transistor Ratio Calculation MOSFET sizing is important Need to have reasonable W/L ratios for circuit to work correctly V OL >VSS but must be low enough to turn off/on next MOSFET in the chain Static current drain when on Vout is a function of the number of parallel and series N channels in the pull down network

33 NMOS Logic Pseudo-NMOS Transistor Ratio Calculation For single supply V OH = Vdd, For the worst case one NMOS to be on 2 V K K Vdd V V Vdd V 2 2 OL P ( ) = ( ) n Tn OL TP K V = K (Vdd V ) 1 1 K OL n T 2 n Assuming that V = V = V V 0 K << K OL p n T Tn Tp p 2 +Vdd A B C D Y

34 NMOS Logic Pseudo-NMOS VTC ( W/L n =1) W/L p = 4 V out [V] W/L p = W/L p = 0.5 W/L p = 0.25 W/L p = V in [V]

35 NMOS Logic Pseudo-NMOS Gates Design for unit current on output PMOS fights NMOS inputs f Y

36 NMOS Logic Pseudo-NMOS Power Pseudo-NMOS draws power whenever Y = 0 Called static power P = I VDD A few ma / gate * 1M gates would be a problem This is why NMOS went extinct! Use Pseudo-NMOS sparingly for wide NORs Turn off PMOS when not in use en A B C Y

37 NMOS Logic Pseudo-NMOS ( NAND) Layout Example Out In1 In2 In3 In4

38 CMOS Logic Static CMOS Logic Family All of the circuits described in the previous sections have a large static power dissipation. This disadvantage can be overcome by using Static CMOS Logic Family

39 CMOS Logic Static CMOS Logic Family NOT +Vdd Vi M2 M1 Vo

40 CMOS Logic Static CMOS Logic Family Two inputs NAND +Vdd M3 M4 Y B M2 A M1

41 CMOS Logic Static CMOS Logic Family Two inputs NOR +Vdd A B Y

42 CMOS Logic Static CMOS Logic Family NAND is more suitable for CMOS because by suppose the equal W/L for NMOS and PMOS transistors, the PMOS transistor has more resistance respect to NMOS, therefore it is better to design circuit by paralleling the PMOS and cascading the NMOS The better Technology for digital circuit is N-Well, because in this Technology the NMOS transistors are made in the Sub. Which result better characteristic for transistor

43 CMOS Logic Realization of More Complicated Gate Circuits a) Y = A(B+C) It can be implemented in three levels: Gate Level Transistor Level Layout Level

44 CMOS Logic Realization of More Complicated Gate Circuits a) Y = A(B+C) Gate Level It consists of 10 transistors, 4 transistors for NOR, 2 for NOT and 4 for NAND B C A Y

45 CMOS Logic Realization of More Complicated Gate Circuits a) Y = A(B+C) Transistor Level It need only 6 transistors A B +Vdd C Y A B C

46 CMOS Logic Realization of More Complicated Gate Circuits a) Y = A(B+C) Layout Level By proper construction of layout, the parasitic capacitors are also reduced and area can be saved

47 CMOS Logic Realization of More Complicated Gate Circuits b) XNOR (Y = AB + AB) Gate Level 16 transistors are needed A Y B

48 CMOS Logic Realization of More Complicated Gate Circuits b) XNOR (Y = AB + AB) Transistor Level (1)» How many transistors are» needed? +Vdd A B B A Y = AB+ AB B B A A

49 CMOS Logic Realization of More Complicated Gate Circuits b) XNOR Transistor Level (2) Previous circuit can be simplified by eliminating two wiring lines A B +Vdd B A Y = AB+ AB B A B A

50 CMOS Logic Realization of More Complicated Gate Circuits b) XNOR Transistor Level (3) In this circuit we have static power dissipation in the state of (A=0,B=1) or (A=1,B=0) +Vdd M3 Y = AB+ AB M1 M2 A B

51 CMOS Logic Realization of More Complicated Gate Circuits b) XNOR Transistor Level (4) (For less dissipation) Note to the state of A = B = Vdd A B Y +Vdd Vdd Vdd 0 M4 M3 Y = AB+ AB Vdd 0 0 M1 M2 Vdd Vdd Vdd-Vth A B

52 CMOS Logic Realization of More Complicated Gate Circuits c) XOR As Previous the Source and Drain of M3 (or M4) are replaced by each other in different states, for example in state of A=0, B=0 the b connection of M3 is Source A B Y + Vdd 0 0 Vdd Vdd 0 Vdd 0 Vdd Vth Vdd-Vth Vdd 0 A M2 M1 B A a M3 a b M4 b Y = AB+ AB

53 CMOS Logic Realization of More Complicated Gate Circuits d) Tri-State Outputs A floating state at the output is needed Non-Inverting En = 1 Y = D En = 0 Y = Hi Z En +Vdd D En Y D Y

54 CMOS Logic Realization of More Complicated Gate Circuits d) Tri-State Outputs A floating state at the output is needed Inverting En = 1 Y = Hi Z En = 0 Y = D D Y En En +Vdd Y D

55 CMOS Logic Realization of More Complicated Gate Circuits e) Schmitt Trigger M3 and M6 have minimum sized geometries With Vin = 0, the transistors M1 and M2 will be on but conducting negligible Drain current since M4 and M5 are off Vin Vx Vy +Vdd M1 M3 M2 Y Vy Vx Vdd M4 Vy Vdd M6 on Vz = Vy V TN Vz M6 M5 +Vdd

56 CMOS Logic Realization of More Complicated Gate Circuits e) Schmitt Trigger When Vin rise to V TN, M5 turns on, but M4 is off. M5 and M6 form an NMOS amplifier. Thus as Vin rises, Vz is falling and in the certain voltage M4 turns on. With both M4 and M5 conducting, Vy rapidly goes to zero turning off M6. With Vy=0, M3 turns on, which aids in turning off M2 as Vx goes from Vdd to Vy-V TP As Vin decrease from Vdd to zero the operation is essentially similar. But now M1 turns on, in different voltage and Vin Vx Vy Vz +Vdd M1 M3 M2 M4 M6 M5 Y +Vdd

57 CMOS Logic Transmission Gates Family Use pass transistors like switches to do logic Inputs drive diffusion terminals as well as gates N transistors instead of 2N No static power consumption Ratioless Bidirectional

58 CMOS Logic Transmission Gates Family NMOS Only Switch Vdd X In 3.0 In Voltage [V] Out x Time [ns]

59 CMOS Logic Transmission Gates Family NMOS Only Switch V B does not pull up to 2.5V, but 2.5-V TN Threshold voltage loss causes (M 2 may be weakly conducting forming a path from Vdd to GND) NMOS has higher threshold than PMOS (body effect)

60 CMOS Logic Transmission Gates Family NMOS Only Switch Pass transistor gates should never be cascaded as on the left Logic on the right suffers from static power dissipation and reduced noise margins

61 CMOS Logic Transmission Gates Family NMOS Only Switch Solution1: Level Restoring Transistor Level Restorer B V dd M r V dd M 2 A M n X Out M 1

62 CMOS Logic Transmission Gates Family NMOS Only Switch Solution1: Level Restoring Transistor Advantages Full swing on x (due to Level Restorer) so no static power consumption by inverter No static backward current path through Level Restorer and PT since Restorer is only active when A is high Restorer adds capacitance, takes away pull down current at X For correct operation Mr must be sized correctly (ratioed)

63 CMOS Logic Transmission Gates Family NMOS Only Switch Solution2: Multiple V T Transistors low V T transistors In 2 = 0V A= 2.5V on Out In 1 = 2.5V off but leaking B= 0V sneak path

64 CMOS Logic Transmission Gates Family NMOS Only Switch Solution2: Multiple V T Transistors Technology solution: Use (near) zero V T devices for the NMOS TGs to eliminate most of the threshold drop (body effect still in force preventing full swing to Vdd) Impacts static power consumption due to subthreshold currents flowing through the TGs (even if VGS is below V T ) In 2 = 0V A= 2.5V on low V T transistors Out In 1 = 2.5V off but leaking B= 0V sneak path

65 CMOS Logic Transmission Gates Family NMOS Only Switch Disadvantage: It can be bad because the signal can be degraded We do not allow a few gates in series for one signal (Pure TG logic is not regenerative, the signal gradually degrades after passing through a number of TGs) Advantage: Allow us to save transistor or less stage of logic A Z B

66 CMOS Logic CMOS Transmission Gates Family PMOS A Y C CMOS C C A Y A Y C C

67 CMOS Logic CMOS Transmission Gates Family There are many symbols for transmission gate B B B A Z A Z A Z OR B' BOOK B' ME A B' Z Be careful, because it is bi-directional

68 CMOS Logic CMOS Transmission Gates Family This circuit performs a function similar to that of the well known diode bridge C = Vss, C = 0 Both transistor are on A = Y The input voltage VA (which must be between Vss and Vdd) is then connected to the output through the parallel on resistance of the channels of the two transistors. As VA approaches Vdd, the N-channel device cuts off but the P-channel device remains non saturated, as VA approaches Vss, the P- channel device cuts off but the N-channel device remains non saturated. Therefore there is always a non saturated transistor between input and output C C A Y A Y C C

69 CMOS Logic CMOS Transmission Gates Family For more understanding note to this circuit We assume: Vy(0 ) = 0, C = Vdd, C = 0, V < Vdd V TP TN VA C Vdd Vy A S D I P I N Y CL t C

70 CMOS Logic CMOS Transmission Gates Family N = sat 0 t t I I I Vy= V = + TP P = sat CL N P N = sat t t t r Vy V PCL = TP Vy= Vdd V τ TN P = triode N = off t t t r Vy Vdd V PCL = TN Vy= Vdd τ P = triode A C I P I N C Y CL

71 CMOS Logic CMOS Transmission Gates Family It is normally assumed as a resistor V (t) A = Vddu(t) C t Vy(t) = Vdd 1 exp u(t) τtg τ = R CL TG TG R = r r TG N P A I P I N C Y CL

72 CMOS Logic CMOS Transmission Gates Family r N and r P are approximately as follow (In saturation region) r r AN N 2 N(Vdd V TN) AP P 2 P(Vdd V TP ) A β β 2V 2V V is Early Voltage R rp VTP RTG = rn rp r N Vdd V TN Vdd Vy

73 CMOS Logic CMOS Transmission Gates Family What to note about TG The inputs must be able to give high current because they are connected directly to Drain and Source of transistors Since each input is connected to an RC circuit, The delay can be considered directly Limited Fan-in Excessive Fan-out Noise vulnerability (not restoring) Supply voltage offset/bias vulnerability Poor high voltage levels if NMOS-only Body effect

74 CMOS Logic CMOS Transmission Gates Family Rules of Thumb Pass-Logic may consume half the power of static logic. But be careful of V T drop resulting in static leakage Pass-Gate Logic is not appropriate when long interconnects separate logic stages or when circuits have high Fan-out load (use buffering)

75 CMOS Logic CMOS Transmission Gates Family AND

76 CMOS Logic CMOS Transmission Gates Family OR Y = A+ AB = (A+ A)(A+ B) = A+ B A A A B A AB Y Wired OR

77 CMOS Logic CMOS Transmission Gates Family MUX A S = 1 Y = B S = 0 S A B S Y S

78 CMOS Logic CMOS Transmission Gates Family MUX S S F F = (In1S+ In2S) V dd GND In 1 S S In 2

79 CMOS Logic CMOS Transmission Gates Family XOR B A B Y = A B B

80 CMOS Logic CMOS Transmission Gates Family XNOR B A B Y = AB+ AB B

81 CMOS Logic CMOS Transmission Gates Family D Latch 1) Load Q = D 2) Hold Q = Q n n n n-1 D LD Q Q LD D LD LD Q LD

82 CMOS Logic CMOS Transmission Gates Family D Latch 1) Load LD = 1 D Q = D D = Q 2) Hold LD = 0 Q Q

83 CMOS Logic CMOS Transmission Gates Family D Latch (Simpler Realization) If in Load Mode a level voltage opposite to the output of weak inverter is applied to the input by TG, Q = D and weak inverter is not damaged! LD D Q LD Q Weak Inverter

84 CMOS Logic Delay in Transmission Gate In V1 V2 Vi V i + 1 V n 1 C C C C C C V n In R eq R V eq 1 V2 R eq V eq eq i V i + 1 V n 1 C C C C C C R R R eq V n In m R eq R eq R eq R eq R eq R eq C C C C C C

85 CMOS Logic Delay Optimization Delay of RC chain n t = 0.69 C R k = 0.69C R P eq eq k= 1 Delay of Buffered chain n(n + 1) 2 n m(m+ 1) n t = 0.69 C R + 1 t m 2 m P e q buf n(m + 1) n = 0.69 C R e q + 1 t 2 m = Pbuf mopt 1.7 CR eq t buf

86 CMOS Logic TG Points to Remember Stored charge leaks away due to reverse-bias leakage current Stored value is good for about 1 ms Value must be rewritten to be valid If not loaded every cycle, must ensure that latch is loaded often enough to keep data valid Capacitance comes primarily from inverter s gate logic

87 CMOS Logic TG Layout

88 CMOS Logic TG Properties Strong pull-up Strong pull-down May be difficult to design into a circuit (layout) because of close proximity of N and P devices (design rule separation) Always requires 2N transisitors for any N x TG design Many logic functions (multiplexers in particular) are easily implemented using TG based designs

89 CMOS Logic Complementary Pass-transistor Logic (CPL) or Differential (+) TG Logic Dual-rail form of pass transistor logic Avoids need for ratioed feedback A A B B A A B B PT Network Inverse PT Network F F F F A B A B S S S S L L Y Y

90 CMOS Logic CPL B B A B A B AND/NAND

91 CMOS Logic 4 Input NAND in CPL

92 CMOS Logic CPL Advantages Differential so complementary data inputs and outputs are always available (so don t need extra inverters) Still static, since the output defining nodes are always tied to Vdd or GND through a low resistance path Design is modular, all gates use the same topology, only the inputs are permuted Simple XOR makes it attractive for structures like adders Fast (assuming number of transistors in series is small)

93 CMOS Logic CPL Disadvantages Additional routing overhead for complementary signals Still have static power dissipation problems V OH is very weak! Then we need an inverter at the output

94 CMOS Logic Differential Cascode Voltage Switch Logic (DCVSL) Compute both true and complementary outputs using a pair of complementary NMOS pull-down network The PMOS transistors are driven by the output of the complementary network No static power consumption Fast response Y Y Inputs f f

95 CMOS Logic Differential Cascode Voltage Switch Logic (DCVSL) Example: NAND/AND Y = AB Y= A+ B A B A Series B

96 Differential Cascode Voltage Switch Logic (DCVSL) General Design F C B A CMOS Logic _ A B C 0 1

97 CMOS Logic Differential Cascode Voltage Switch Logic (DCVSL) General Design a b a b x _ + x x x _ + u u = ax+ bx u u u a b a b a b x _ + _ + x _ + u 1 u 2 u 1 u 2

98 CMOS Logic Differential Cascode Voltage Switch Logic (DCVSL) General Design 0 1 C 0 1 _ + _ + _ + _ + C _ + _ + B A _ + _ + _ + B A _ + + +

99 CMOS Logic Differential Cascode Voltage Switch Logic (DCVSL) Example: XOR/XNOR

100 CMOS Logic Rules of Thumb Step-up (alpha) ratio of 2.7 ( e ) produces minimum powerdelay product P vs. N (beta) ratio of 2 balances pull-up and pull-down times and noise margins Approximately 75% of static logic are NAND stacks (limit stack to 3-4, use ordering and tapering for speed) Glitches consume approximately 15% of overall chip power Crossover (short-circuit) current consumes ~ 10% of a static chip s total power (but is a function of input/output slews, ie sizing)

101 Summary This lecture describes the basic MOS Logic Gates which require no clock or other periodic signal for operation and also implementation of them in three following levels Gate Level Transistor level Layout Level

102 Contents Introduction Dynamic CMOS Logic CMOS Domino Logic CD Domino Logic Dynamic CVSL Sample-Set Differential Logic (SSDL) Summary

103 Introduction As mentioned before Digital MOS circuits can be classified into two categories: Static Circuits: require no clock or other periodic signal for operation (except sequential logic). In these circuits at every point in time (except when switching) the output is connected to either GND or Vdd via a low resistance path fan-in of N requires 2N devices (n N-type + n P-type) Dynamic Circuits: require periodic clock signals, synchronized with data signals, for proper operation even in combinational logic. These circuits rely on the temporary storage of signal values on the (parasitic) capacitance of high impedance nodes requires only N + 2 transistors (n+1 N-type + 1 P-type) takes a sequence of precharge and conditional evaluation phases to realize logic functions

104 Introduction Why Dynamic Logic? In the area of high speed, higher Fan-in, extremely low power dissipation, other digital logic circuit have been considered. In this lecture, two of these alternatives to CMOS are described. The circuits are basically NMOS or CMOS Gates with slight improvements. These are: Dynamic CMOS Logic CMOS Domino Logic Each of them have specific operating advantages over NMOS or CMOS, but exhibit disadvantages in other areas

105 Dynamic CMOS Logic Dynamic Gates use a clocked PMOS pullup Two modes: precharge and evaluate φ Precharge Evaluate Precharge Y

106 Dynamic CMOS Logic The Foot What if pulldown network is ON during precharge? Use series evaluation transistor to prevent fight φ A Y precharge transistor foot

107 Dynamic CMOS Logic Dynamic CMOS Logic To make the gate dynamic, a clock pulse is applied to the gate of complementary P and N channel devices. This gate consists of an NMOS Logic circuit whose output node is precharged to Vdd by the PMOS, when the clock is zero. The output node is discharged by the NMOS transistor connected to ground when the clock is high CLK P CLK NMOS Logic Circuit N CLK

108 Dynamic CMOS Logic Dynamic CMOS Logic M p 1 L 2 3 M e Precharge (Clk = 0) Evaluate (Clk = 1)

109 Dynamic CMOS Logic Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation Inputs to the gate can make at most one transition during evaluation Output can be in the high impedance state during and after evaluation (PDN off), state is stored on C L

110 Dynamic CMOS Logic Canonical Forms

111 Dynamic CMOS Logic Properties of Dynamic Gates Logic function is implemented by the PDN only should be smaller in area than static complementary CMOS Full swing outputs (V OL = GND and V OH = V DD ) Nonratioed - sizing of the devices is not important for proper functioning (only for performance) Faster switching speeds reduced load capacitance due to lower number of transistors per gate (C int ) so a reduced logical effort reduced load capacitance due to smaller fan-out (C ext ) no I sc, so all the current provided by PDN goes into discharging C L Ignoring the influence of precharge time on the switching speed of the gate, t plh = 0 but the presence of the evaluation transistor slows down the t phl

112 Dynamic CMOS Logic Properties of Dynamic Gates Power dissipation should be better consumes only dynamic power no short circuit power consumption since the pull-up path is not on when evaluating lower C L - both C int (since there are fewer transistors connected to the drain output) and C ext (since there the output load is one per connected gate, not two) But power dissipation can be significantly higher due to higher transition probabilities extra load on CLK PDN starts to work as soon as the input signals exceed V Tn, so set V M, V IH and V IL all equal to V Tn low noise margin (NM L ) Needs a precharge/evaluate clock

113 Dynamic CMOS Logic Leakage Sources Subthreshold conduction Transistors can t abruptly turn ON or OFF Reverse-biased PN junction diode current I s depends on doping levels And area and perimeter of diffusion regions, typically < 1 fa/µm 2 Gate Leakage Carriers may tunnel thorough very thin gate oxides Negligible for older processes 10 9 t ox 10 6 V DD trend 0. 6 nm 0. 8 nm nm 1. 2 nm V DD 1. 5 nm 1. 9 nm

114 Dynamic CMOS Logic Leakage Sources Output settles to an intermediate voltage determined by a resistive divider of the pull-up and pull-down networks Once the output drops below the switching threshold of the fan-out logic gate, the output is interpreted as a low voltage 2.5 CLK Voltage (V) Out Time (ms)

115 Dynamic CMOS Logic Leakage Sources Subthreshold leakage is dominant in modern transistors CLK p L e V Out Precharge Evaluate Leakage sources

116 Dynamic CMOS Logic Solution to Charge Leakage M p M kp L M e

117 Dynamic CMOS Logic Charge Sharing Charge stored originally on CY is redistributed (shared) over CX leading to static power consumption by downstream gates and possible circuit malfunction When Vout = - Vdd (CX / (CX + CY )) the drop in Vout is large enough to be below the switching threshold of the gate it drives causing a malfunction φ φ A x Y C Y A Y Charge sharing noise B = 0 C x x CY V = V = V C + C x Y dd x Y

118 Dynamic CMOS Logic Solution to Charge Redistribution Add secondary precharge transistors (at the cost of increased area and power) Typically need to precharge every other node Secondary precharge transistors should be small because their diffusion capacitance slows the evaluation (increase delay) Big load capacitance C Y helps as well A B x Y secondary precharge transistor

119 Dynamic CMOS Logic Charge Sharing Example What is the worst case voltage drop on y? (Assume all inputs are low during precharge and that all internal nodes are initially at 0V)

120 Dynamic CMOS Logic Charge Sharing Example ( a c) ( a c y) ( ( )) Vout = Vdd C + C C + C + C = 2.5V = 0.94V CLK y = A B C Load inverter a A A C y =50fF y C a =15fF B B B c b B d C b =15fF C c =15fF C C C d =10fF CLK

121 Dynamic CMOS Logic Backgate Coupling Susceptible to crosstalk due to High impedance of the output node Capacitive coupling Out2 capacitively couples with Out1 through the gate-source and gatedrain capacitances of M4 CLK M p Out1 =1 M 6 M 5 Out2 =0 A=0 M 1 C L1 M 4 C L2 B=0 M 2 M 3 In CLK M e Dynamic NAND Static NAND

122 Dynamic CMOS Logic Backgate Coupling Capacitive coupling means Out1 drops significantly so Out2 doesn t go all the way to ground 3 Due to clk feedthrough Voltage 2 1 Clk Out1 Due to backgate 0 In Out Time, ns

123 Dynamic CMOS Logic Clock Feedthrough A special case of capacitive coupling between the clock input of the precharge transistor and the dynamic output node due to the gate to drain capacitance So voltage of Out can rise above Vdd. The fast rising (and falling edges) of the clock couple to Out M p M e L

124 Voltage Dynamic CMOS Logic Clock Feedthrough Clock feedthrough In & Clk Out Time, ns 1 Clock feedthrough

125 Dynamic CMOS Logic Other Effects Capacitive coupling Substrate coupling Minority charge injection Supply noise (Ground bounce) Floating output nodes

126 Dynamic CMOS Logic Floating output nodes Solutions: Only connect to gates Add staticizer to refresh the charge s 0 0 s

127 Dynamic CMOS Logic Advantages: For n inputs, dynamic logic requires n+2 transistors have small area, high speed and compact layouts CLK P CLK Disadvantages: Circuit operation is more complex due to the required clock The inputs can only change during the precharge phase and must be stable during the evaluate portion of the cycle NMOS Logic Circuit N CLK Need Monotonicity can not be cascaded

128 Dynamic CMOS Logic Monotonicity Dynamic gates require monotonically rising inputs during evaluation A violates monotonicity during evaluation φ φ Precharge Evaluate Precharge A Y Output should rise but does not

129 Dynamic CMOS Logic Monotonicity Woes Dynamic gates produce monotonically falling outputs during evaluation Illegal for one dynamic gate to drive another! A 1 = Precharge Evaluate Precharge X X monotonically falls during evaluation Y Y should rise but cannot

130 Dynamic CMOS Logic Cascading V Clk In Out1 V Tn Out2 V Only 0 1 transitions allowed at inputs! t

131 Dynamic CMOS Logic Cascading Input going from high to low during evaluation a is 5V when precharge b = 5V, c = 5V During evaluation: Wanted: b 0V, c 5V But, b takes some time to drop to 0V Consequently, c may fall to some unknown value Solution NP-CMOS NORA Logic Domino logic a b c

132 Dynamic CMOS Logic NP-CMOS Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN Clk In 1 In 2 In 3 Clk M p PDN Me Out1 Clk In 4 In 5 Clk M e PUN M p Out2 (to PDN)

133 Dynamic CMOS Logic NORA Logic WARNING: Very sensitive to noise! Clk In 1 In 2 In 3 Clk M p PDN M e Out1 Clk In 4 In 5 Clk M e PUN M p Out2 (to PDN) to other PDN s to other PUN s

134 Dynamic CMOS Logic An example

135 Dynamic CMOS Logic Dynamic 4 Input NAND Gate V DD Out In 1 In 2 In 3 In 4 φ GND

136 Dynamic CMOS Logic Power Consumption Power only dissipated when previous Out = 0 p 1 L 2 3 e

137 Dynamic CMOS Logic Power Consumption Dynamic Power Consumption is Data Dependent Assume signal probabilities (Dynamic 2-input NOR Gate) P A=1 = 1/2 P B=1 = 1/2 A B Out Then transition probability P 1 0 = P out=0 = ¾ Switching activity can be higher in dynamic gates!

138 Dynamic CMOS Logic Rules of Thumb Dynamic logic is best for wide OR/NOR structure (e.g. bitlines), providing 50% delay improvement over static CMOS Dynamic logic consumes 2x power due to its phase activity (unconditional pre-charging), not counting clock power

139 Dynamic CMOS Logic Notes No need to implement the complement of the function, leading to smaller area We can avoid the long PMOS chains Handle the charge sharing problem and floating output nodes Input transistors should not change from on to off during evaluation

140 CMOS Domino Logic It is an extension of dynamic CMOS gates that allow cascading of stages The simple modification entails incorporating a static CMOS inverter at the output of each logic gate In 1 In 2 Clk M p PDN Out1 Clk In 4 M p M kp PDN Out2 A B domino AND W X Y Z C In 3 In 5 φ Clk Me Clk Me dynamic NAND static inverter

141 CMOS Domino Logic Stage A should be precharged in Φ 1 and evaluate in Φ 2 Stage B should be precharged in Φ 2 and evaluate in Φ 1

142 CMOS Domino Logic During precharge (clk=0), the output node of the dynamic gate is precharged high and the output node of the CMOS inverter is low. Then subsequent stages will be turned off during the precharge phase When the clk=1, the output of the driving gate will conditionally discharge, allowing the output of the inverter to conditionally go high. Each connected gate output can then make a transition from low-to-high, in sequence There is no restriction on the number of logic stages that can be cascaded provided that all stages can evaluate during one clock pulse

143 CMOS Domino Logic pc = Φ 1 and ev = Φ 2 pc pc = 1 ev = 2 cycle V W n- network X Y 1 1 ev 2 2 precharge input latched here evaluate output latched here

144 CMOS Domino Logic Won t work! If pc = Φ 2 and ev = Φ 1 pc = 2 ev = 1 cycle 1 2 evaluate precharge input latched here evaluate output latched here precharge

145 CMOS Domino Logic Why Domino? Like falling dominos!

146 CMOS Domino Logic Produces monotonic outputs φ Precharge Evaluate Precharge domino AND W W X Y Z X A B C Y φ Z dynamic NAND static inverter A B φ W H C X φ Y H φ A X Z = B C φ Z

147 CMOS Domino Logic Domino Optimizations Each domino gate triggers next one, like a string of dominos toppling over Gates evaluate sequentially but precharge in parallel Thus evaluation is more critical than precharge HI-skewed static stages can perform logic Static inverter can be optimized to match fan-out φ S0 S1 S2 S3 D0 D1 D2 D3 φ H Y S4 S5 S6 S7 D4 D5 D6 D7

148 CMOS Domino Logic Leakage Dynamic node floats high during evaluation Transistors are leaky (I OFF 0) Dynamic value will leak away over time Formerly miliseconds, now nanoseconds! Use keeper to hold dynamic node Must be weak enough not to fight evaluation weak keeper φ A 1 k 2 X H Y 2

149 CMOS Domino Logic Noise Sensitivity Dynamic gates are very sensitive to noise Inputs: V IH V tn Outputs: floating output susceptible noise Noise sources Capacitive crosstalk Charge sharing Power supply noise Feedthrough noise And!

150 CMOS Domino Logic Designing with Domino Logic If all the inputs come from other domino gates, then all the inputs will be low during the precharge. You don t need to explicit evaluate transistor Need to be a little careful. When precharge begins, the first gate s output must precharge before the next gate can precharge. Both evaluate and precharge ripple in this scheme. But, if there is already a tall stack, transistor ratioing will let precharge win anyway. (but you waste power until the precharge ripples)

151 CMOS Domino Logic Example During precharge, x, y, z = 1, x, y = 0 During evaluation, x = 0 when a = b = 1 Therefore, z = abcd a x x y y z b c d

152 CMOS Domino Logic Advantages: Large Fan-in, fewer transistors (n+4 transistors, whereas CMOS requires 2n) Single clock can be used to precharge and evaluate all stages at the same time It is attractive for high-speed circuits 1.5 2x faster than static CMOS Widely used in high-performance microprocessors Disadvantages: Each logic block must incorporate a separate inverter Each block performs only non-inverting logic Monotonicity Leakage Charge sharing Noise

153 CMOS Domino Logic Dual Rail Domino Domino only performs noninverting functions AND, OR but not NAND, NOR, or XOR Dual-rail domino solves this problem Takes true and complementary inputs Y_l inputs f φ φ f Y_h Produces true and complementary outputs sig_h sig_l Meaning Precharged 0 1 invalid

154 CMOS Domino Logic Example AND/NAND Given A_h, A_l, B_h, B_l Compute Y_h = A * B, Y_l = ~(A * B) Pulldown networks are conduction complements Y_l = A*B φ A_h Y_h = A*B A_l B_l B_h φ

155 CMOS Domino Logic Example XOR/XNOR Sometimes possible to share transistors Y_l = A xnor B A_h A_l φ A_l A_h Y_h = A xor B B_l B_h φ

156 CMOS Domino Logic Rules of Thumb Typical domino keepers have W/L = 5-20% of effective width of evaluate tree Typical domino output buffers have a beta ratio of ~ 6:1 to push the switch point higher for fast rise-time

157 CD Domino Logic We noted that dynamic inputs never make 1 to 0 transitions while in evaluation Two solutions: Precharge outputs low using an inverting gate (standard domino) Delay the evaluate clock until inputs settle (CD domino)

158 CD Domino Logic Self-timed dynamic logic family Consists of a dynamic gate, and an optional delay element for the clock signal Mpre Out = a+b a b clk(i) Meval delay clk(i+1)

159 CD Domino Logic Advantages Uses single-rail circuits, rather than dual-rail for standard domino Provides both inverting and non-inverting functions High-speed, large fan-in NOR and OR circuits

160 CD Domino Logic Delay Matching CD domino requires delay matching between the slowest dynamic gate at a level and a delay element A 20% margin is typically added to the delay of the fixed delay element to account for PVT variations Thus, 20% of the speed gain possible with CD domino is not realized Average speed gain of (60+20)% is theoretically possible Use digitally programmable delay elements (PDEs) to reduce the margin and attain a speed improvement without affecting the reliability in the presence of variations

161 CD Domino Logic Clocking Scheme The circuits are fully levelized The delay element on each level is tuned to the slowest gate at its level, plus a 20% margin (other gates). dynamic gate (other gates). dynamic gate (other gates). dynamic gate primary inputs dynamic gate dynamic gate dynamic gate clk1 fixed delay clk2 fixed delay clk3 fixed delay clk4 gate level gate level gate level 1 2 3

162 Dynamic CVSL Positive feedback does not exist F F C In { NMOS Logic Array }In C

163 Sample-Set Differential Logic (SSDL) It is one type of Dynamic CVSL with positive feedback By this logic the low level output is guaranteed to zero in evaluation phase F C C F In { NMOS Logic Array }In

164 Summary This lecture describes many basics CMOS Logic Gates which require clock or other periodic signal for operation These circuits rely on the temporary storage of signal values on the (parasitic) capacitance of high impedance nodes