Integrated Circuits & Systems
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1 Federal University of Santa atarina enter for Technology omputer Science & Electronics Engineering Integrated ircuits & Systems INE 5442 Lecture 16 MOS ombinational ircuits - 2 guntzel@inf.ufsc.br
2 Pass Transistor Logic Primary inputs may drive gate terminals of transistor as well as source-drain terminals 0 F =. Ensures a low impedance path to supply rail when =0 (this is a static gate!) Target: Fewer transistors per logic function than complementary MOS (lower capacitance) asic problem: NMOS transistors are not effective at passing 1 s. Reduced noise margins Static power dissipation Slide 17.2
3 Pass Transistor Logic 3.0 In V x = V DD V Tn Voltage [V] Out x Due to the body effect, Vx does not achieve V DD Message: do not cascade pass transistors Time [ns] Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.3
4 Pass Transistor Logic: Simulation 1 File passtrans1.cir ( ) Vdd Vdd a MN2 MP1 MN1 out L x Slide 17.4
5 Pass Transistor Logic: Simulation 1 Resulting Simulation Waveforms Slide 17.5
6 Pass Transistor Logic: Simulation 2 reate a file passtrans2.cir by modifying file passtrans1.cir Vdd a b MP1 Vdd MN2 MN3 MN1 out L x y Slide 17.6
7 Pass Transistor Logic: Simulation 2 Resulting Simulation Waveforms Slide 17.7
8 Pass Transistor Logic Design Guidelines Vdd Vdd a MN1 Vx=Vdd-V Tn1 MN2 out Vdd a MN1 b MN2 out Vy=Vdd-V Tn1 Vy=Vdd-V Tn1 -V Tn2 Slide 17.8
9 Pass Transistor Logic Example 1: 2:1 multiplexer Simplified behavior: = if = 1 sel sel Y 0 1 Y Slide 17.9
10 Pass Transistor Logic pplication: FPG LUT S0 S1 S2 S3 F S4 S5 S6 S7 Slide 17.10
11 Pass Transistor Logic Example 2: random function (4 input variables) buffer F E1 0 0 E1 F 0 1 E1 1 0 E1 E2 1 1 E2 F = E2 + E1 + E1 N transistors No static power consumption Slide 17.11
12 Example 3: XOR MOS ombinational ircuits Pass Transistor Logic s a controlled inverter X X Y X Y Y X Y X Y = X Y + X Y Only 4 transistors! However, it suffers from signal degradation Slide 17.12
13 omplementary Pass Transistor Logic (PL or DPL) Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.13
14 Pass Transistor Logic Level-Restoring V DD Level Restorer M r V DD M 2 M n X Out M 1 Source: Rabaey; handrakasan; Nikolic, 2003 dvantage: Full Swing Restorer adds capacitance, takes away pull down current at X Ratio problem Slide 17.14
15 Pass Transistor Logic Restorer sizing V o l t a g e [V] W / L r =1.75/0.25 W / L r =1.50/0.25 W / L r =1.0/0.25 W / L r =1.25/0.25 Upper limit on restorer size Pass-transistor pull-down can have several transistors in stack Time [ps] Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.15
16 Transmission Gate Simplified behavior: = if = 1 circuit Symbolic representation Requires an inverter to generate Number of transistors: 2+2=4 Slide 17.16
17 Transmission Gate Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.17
18 Transmission Gate: Simulation 1 File tg-drenofixo.cir ( ) Vdd a Vdd Vdd MN1 MP1 out a MP1 b MP1 x MN1 L MN1 Slide 17.18
19 Transmission Gate: Simulation 1 Resulting Simulation Waveforms b a x out Slide 17.19
20 Transmission Gate: Simulation 2 Modify file tg-drenofixo.cir to create file tg-drenopulso.cir as shown below Vdd Vdd Vdd a MP1 b MN1 MP1 out MN1 MP1 Gnd x MN1 L Slide 17.20
21 Transmission Gate: Simulation 2 Resulting Simulation Waveforms b a x tp=~26ps out Slide 17.21
22 Transmission Gate Multiplexer - Layout V DD S S GND Source: Rabaey; handrakasan; Nikolic, 2003 In 1 S S In 2 Slide 17.22
23 Transmission Gate XOR version 1 s a controlled inverter = + Requires twice as transistors as the pass transistor-based one, but still a small amount (8) More robust than the the pass transistor-based version Slide 17.23
24 Transmission Gate XOR version 2 Requires only 6 transistors if =1, F= (M1 & M2 act as an inverter) if =0, F= M = + M1 F M3/M4 Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.24
25 Delay in Transmission Gate Networks In V 1 V i-1 V i V i+1 V n-1 V n (a) In R eq R V eq R eq R 1 V i V i+1 V eq n-1 V n m (b) R eq R eq R eq R eq R eq R eq In Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.25
26 Delay Optimization Slide 17.26
27 Transmission Gate Full dder Similar delays for sum and carry Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.27
28 ell Design MOS ombinational ircuits Standard ells General purpose logic an be synthesized Same height, varying width Datapath ells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.28
29 Standard ell Methodology (1980 s) Routing channel V DD signals GND Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.29
30 Standard ell Methodology (1980 s) Mirrored ell No Routing channels V DD V DD M2 M3 Source: Rabaey; handrakasan; Nikolic, 2003 Mirrored ell Slide GND GND
31 Standard ells N Well V DD ell height 12 metal tracks Metal track is approx. 3λ + 3λ Pitch = repetitive distance between objects ell height is 12 pitch 2λ In Out ell boundary GND Rails ~10λ Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.31
32 Standard ells MOS ombinational ircuits With minimal diffusion routing V DD With silicided diffusion V DD In Out In Out Source: Rabaey; handrakasan; Nikolic, 2003 GND Slide GND
33 Standard ells MOS ombinational ircuits V DD 2-input NND gate Out GND Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.33
34 Sticks Diagram MOS ombinational ircuits ontains no dimensions Represents relative positions of transistors Inverter V DD NND2 V DD Out Out GND In GND Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.34
35 Sticks Diagram j Logic Graph X PUN X = ( + ) X i V DD i j GND PDN Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.35
36 Two Versions of ( + ) V DD V DD X X GND GND Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.36
37 onsistent Euler Path X X i V DD j GND Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.37
38 OI22 Logic Graph X PUN D D X = (+) (+D) X V DD D D GND PDN Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.38
39 Multi-Fingered Transistors One finger Two fingers (folded) Less diffusion capacitance Source: Rabaey; handrakasan; Nikolic, 2003 Slide 17.39
40 MOS ombinational References ircuits 1. REY, J; HNDRKSN,.; NIKOLI,. Digital Integrated ircuits: a design perspective. 2 nd Edition. Prentice Hall, ISN: WESTE, Neil; HRRIS, David. MOS VLSI Design: a circuits and systems perspective. ddison-wesley, 4 th Edition, ISN Slide 17.40
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