EE 330 Lecture 5. Other Logic Styles Improved Device Models Stick Diagrams

Transcription

1 EE 330 Lecture 5 Other Logic Styles Improved evice Models Stick iagrams

2 Review from Last Time MOS Transistor Qualitative iscussion of n-channel Operation ulk Source Gate rain rain Gate n-channel MOSFET Source Equivalent Circuit for n-channel MOSFET G = 0 G = 1 Source assumed connected to ground S S This is the first model we have for the n-channel MOSFET!

3 Review from Last Time MOS Transistor Qualitative iscussion of p-channel Operation Source Gate rain rain ulk Gate p-channel MOSFET Source Equivalent Circuit for p-channel MOSFET S G = 0 S G = 1 Source assumed connected to V and oolean G at gate is relative to ground This is the first model we have for the p-channel MOSFET!

4 Review from Last Time MOS Transistor Comparison of Operation rain rain Gate Gate Source Source G = 0 G = 1 G = 0 G = 1 S S S S

5 Review from Last Time Pull-up and Pull-down Networks Three key characteristics of Static CMOS Gates 1. PU network comprised of p-channel devices 2. P network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time Three properties of Static CMOS Gates (based upon simple switch-level model) 1. V H =V, V L =0 (too good to be true?) X n V PUN PN 2. P H =P L =0 (too good to be true?) 3. t HL =t LH =0 (too good to be true?) These 3 properties are inherent in oolean circuits with these 3 characteristics

6 Example 1: How many transistors are required to realize the function F C in a basic CMOS process if static NN and NOR gates are used? ssume, and C are available.

7 Example 1: How many transistors are required to realize the function F C in a basic CMOS process if static NN and NOR gates are used? ssume, and C are available. Solution: C F 20 transistors and 5 levels of logic

8 How many transistors are required to realize the function in a basic CMOS process if static NN and NOR gates are used? ssume, and C are available. C F Solution (alternative): From basic oolean Manipulations C C F C 1 F F 8 transistors and 3 levels of logic Example 1:

9 Example 1: How many transistors are required to realize the function F C in a basic CMOS process if static NN and NOR gates are used? ssume, and C are available. Solution (alternative): From basic oolean Manipulations F 1 C F F 6 transistors and 2 levels of logic

10 Example 2 C Standard Static CMOS Implementation C 3 levels of Logic 16 Transistors if asic CMOS Gates are Used

11 Example 3: XOR Function = widely-used 2-input Gate Static CMOS implementation = + 22 transistors 5 levels of logic elays unacceptable and device count is too large!

12 Consider again Example 2: C Standard Static CMOS Implementation C 3 levels of Logic 16 Transistors if asic CMOS Gates are Used Can the same oolean functionality be obtained with less transistors?

13 Observe: V C C C Significant reduction in transistor count and levels of logic for realizing same oolean function Termed a Complex Logic Gate implementation Some authors term this a compound gate

14 Complex Logic Gates Pull-up Network C V Pull-down Network C C

15 Complex Gates V Pull up and pull down network never both conducting One of the two networks is always conducting C C

16 Complex Gates Nomenclature: V PUN X n PN When the logic gate shown is not a multiple-input NN or NOR gate but has Characteristics 1, 2, and 3 above, the gate will be referred to as a Complex Logic Gate Complex Logic Gates also implement static logic functions and some authors would refer to this as Static CMOS Logic as well but we will make the distinction and refer to this as Complex Logic Gates

17 Complex Gates V PUN X n PN Complex Gate esign Strategy: 1. Implement in the PN 2. Implement in the PUN (must complement the input variables since p- channel devices are used) ( and expressed as either SOP or POS form)

18 XOR in Complex Logic Gates = Need and in standard SOP or POS form

19 XOR in Complex Logic Gates = = + = + = = + +

20 XOR in Complex Logic Gates = + = + + PN PUN

21 XOR in Complex Logic Gates V = + = transistors and 2 levels of logic Notice a significant reduction in the number of transistors required

22 XOR in Complex Logic Gates = + = + + Multiple PU and P networks can be used =

23 Complex Logic Gate Summary: V PUN X n PN If PUN and PN satisfy the characteristics: 1. PU network comprised of p-channel device 2. P network comprised of n-channel device 3. One and only one of these networks is conducting at the same time Properties of PU/P logic of this type (with simple switch-level model): Rail to rail logic swings Zero static power dissipation in both =1 and =0 states rbitrarily fast (too good to be true? will consider again with better model)

24 Consider Standard CMOS Implementation 2 levels of Logic 6 Transistors if asic CMOS Gates are Used asic noninverting functions generally require more complexity if basic CMOS gates are used for implementation

25 Pass Transistor Logic V R Requires only 2 transistors rather than 6 for a standard CMOS gate (and a resistor).

26 Pass Transistor Logic R Even simpler pass transistor logic implementations are possible Requires only 1 transistor (and a resistor).

27 Pass Transistor Logic R 6 transistors, 1 resistor, two levels of logic (the 4 transistors in the two inverters are not shown)

28 Pass Transistor Logic R R 2 transistors, 1 resistor, one level of logic

29 Pass Transistor Logic R Requires only 1 transistor (and a resistor) - Pass transistor logic can offer significant reductions in complexity for some functions (particularly noninverting) - Resistor may require more area than several hundred or even several thousand transistors - Signal levels may not go to V or to 0V - Static power dissipation may not be zero - Signals may degrade unacceptably if multiple gates are cascaded - resistor often implemented with a transistor to reduce area but signal swing and power dissipation problems still persist - Pass transistor logic is widely used

30 Logic esign Styles Several different logic design styles are often used throughout a given design (3 considered thus far) Static CMOS Complex Logic Gates Pass Transistor Logic The designer has complete control over what is placed on silicon and governed only by cost and performance New logic design strategies have been proposed recently and others will likely emerge in the future The digital designer needs to be familiar with the benefits and limitations of varying logic styles to come up with a good solution for given system requirements

31 MOSFET Modeling Simple model of MOSFET was developed Simple gates designed in CMOS Process were introduced Some have zero power dissipation Some have or appeared to have rail to rail logic voltage swings ll appeared to be Infinitely fast Logic levels of some can not be predicted with simple model Simple model is not sufficiently accurate to provide insight relating to some of these properties MOSFET modeling strategy hierarchical model structure will be developed generally use simplest model that can be justified

32 MOS Transistor Models 1, Switch-Level model rain rain Gate Gate Source Source G = 0 G = 1 G = 0 G = 1 dvantages: Simple, does not require understanding of semiconductor properties, does not depend upon process, adequate for understanding basic operation of many digital circuits S S S S Limitations: oes not provide timing information (surfaced when looking at static CMOS circuits, and several others that have not yet become apparent from the applications that have been considered) and can not support design of resistor used in Pass Transistor Logic

33 End of Lecture 5