EE40 Lecture 35. Prof. Chang-Hasnain. 12/5/07 Reading: Ch 7, Supplementary Reader

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1 EE4 Lecture 35 2/5/7 Reading: Ch 7, Supplementary Reader EE4 all 26 Slide Week 5 OUTLINE Need for Input Controlled Pull-Up CMOS Inverter nalysis CMOS Voltage Transfer Characteristic Combinatorial logic circuits Logic inary representations Combinatorial logic circuits Reading Chap Supplementary Notes Chapter 4 EE4 all 26 Slide 2

2 2 Digital Circuits Introduction nalog: signal amplitude is continuous with time. Digital: signal amplitude is represented by a restricted set of discrete numbers. inary: only two values are allowed to represent the signal: High or low (i.e. logic or ). Digital word: Each binary digit is called a bit series of bits form a word yte is a word consisting of 8-bits dvantages of digital signal Digital signal is more resilient to noise can more easily differentiate high () and low () Transmission Parallel transmission over a bus containing n wires. aster but short distance (internal to a computer or chip) Serial transmission (transmit bits sequentially) Longer distance EE4 all 26 Slide 3 nalog vs. Digital Signals Most (but not all) observables are analog think of analog vs. digital watches but the most convenient way to represent & transmit information electronically is to use digital signals think of telephony nalog-to-digital (/D) & digital-to-analog (D/) conversion is essential (and nothing new) think of a piano keyboard EE4 all 26 Slide 4

3 3 nalog Signal Example: Microphone Voltage V in microvolts Voltage with normal piano key stroke 5 microvolt 44 Hz signal t in milliseconds V in microvolts Voltage with soft pedal applied 25 microvolt 44 Hz signal t in milliseconds 5 microvolt 22 Hz signal V in microvolts t in milliseconds nalog signal representing piano key, below middle C (22 Hz) EE4 all 26 Slide 5 Digital Signal Representations inary numbers can be used to represent any quantity. We generally have to agree on some sort of code, and the dynamic range of the signal in order to know the form and the number of binary digits ( bits ) required. Example : Voltage signal with maximum value 2 Volts inary two () could represent a 2 Volt signal. To encode the signal to an accuracy of part in 64 (.5% precision), 6 binary digits ( bits ) are needed Example 2: Sine wave signal of known frequency and maximum amplitude 5 µv; µv resolution needed. EE4 all 26 Slide 6

4 4 Decimal Numbers: ase Digits:,, 2, 3, 4, 5, 6, 7, 8, 9 Example: 327 = (3x 3 ) + (2x 2 ) + (7x ) + (x ) This is a four-digit number. The left hand most number (3 in this example) is often referred as the most significant number and the right most the least significant number ( in this example). EE4 all 26 Slide 7 Numbers: positional notation Number ase symbols per digit: ase (Decimal):,, 2, 3, 4, 5, 6, 7, 8, 9 ase 2 (inary):, Number representation: d 3 d 3... d d is a 32 digit number value = d d d + d inary:, (In binary digits called bits ) = = = 26 Here 5 digit binary # turns into a 2 digit decimal # EE4 all 26 Slide 8

5 5 Hexadecimal Numbers: ase 6 Hexadecimal:,, 2, 3, 4, 5, 6, 7, 8, 9,,, C, D, E, Normal digits + 6 more from the alphabet Conversion: inary Hex hex digit represents 6 decimal values 4 binary digits represent 6 decimal values hex digit replaces 4 binary digits EE4 all 26 Slide 9 Digital Signal Representations inary numbers can be used to represent any quantity. We generally have to agree on some sort of code, and the dynamic range of the signal in order to know the form and the number of binary digits ( bits ) required. Example : Voltage signal with maximum value 2 V and minimum of V. inary two () could represent a 2 Volt signal. To encode the signal to an accuracy of part in 64 (.5% precision), 6 binary digits ( bits ) are needed Example 2: Sine wave signal of known frequency and maximum amplitude 5 µv; µv resolution needed. EE4 all 26 Slide

6 6 Resolution The size of the smallest element that can be separated from neighboring elements. The term is used to describe imaging systems, the frequency separation achieved by spectrometers, and so on. EE4 all 26 Slide Decimal-inary Conversion Decimal to inary Repeated Division y 2 Consider the number 267. Subtraction if you know your 2 N values by heart. inary to Decimal conversion 2 = x2 5 +x2 4 +x2 3 +x2 2 + x2 + x2 = = 49 = 4x + 9x EE4 all 26 Slide 2

7 7 Example 2 (continued) Possible digital representation for the sine wave signal: nalog representation: Digital representation: mplitude in µv inary number EE4 all 26 Slide 3 inary Representation N bit can represent 2 N values: typically from to 2 N - 3-bit word can represent 8 values: e.g.,, 2, 3, 4, 5, 6, 7 Conversion Integer to binary raction to binary (3.5 =. 2 and.392 =. 2 ) Octal and hexadecimal EE4 all 26 Slide 4

8 8 Logic gates Combine several logic variable inputs to produce a logic variable output Memory Memoryless: output at a given instant depends the input values of that instant. Momory: output depends on previous and present input values. EE4 all 26 Slide 5 oolean algebras lgebraic structures "capture the essence" of the logical operations ND, OR and NOT corresponding set for theoretic operations intersection, union and complement named after George oole, an English mathematician at University College Cork, who first defined them as part of a system of logic in the mid 9th century. oolean algebra was an attempt to use algebraic techniques to deal with expressions in the propositional calculus. Today, oolean algebras find many applications in electronic design. They were first applied to switching by Claude Shannon in the 2th century. EE4 all 26 Slide 6

9 9 oolean algebras The operators of oolean algebra may be represented in various ways. Often they are simply written as ND, OR and NOT. In describing circuits, NND (NOT ND), NOR (NOT OR) and XOR (exclusive OR) may also be used. Mathematicians often use + for OR and for ND (since in some ways those operations are analogous to addition and multiplication in other algebraic structures) and represent NOT by a line drawn above the expression being negated. EE4 all 26 Slide 7 oolean lgebra NOT operation (inverter) i = ND operation + = i = i = i = i = i OR operation ( i) ic = i( ic) + = + = + = + = + ( + ) + C = + ( + C) EE4 all 26 Slide 8

10 Graphic Representation i = + = ull square = complete set = Yellow part = NOT() = White circle = EE4 all 26 Slide 9 Graphic Representation +! = + = ( + ) i( + ) = i + + Exclusive OR=yellow and blue part intersection/overlap part =exactly when only one of the input is true EE4 all 26 Slide 2

11 oolean lgebra Distributive Property i( + C) = i + ic ( + ) ic = ( + ) i( + C) De Morgan s laws + = i i = + n excellent web site to visit EE4 all 26 Slide 2 Examples = C + C + (C+D) (D+E) = C (+D+E) + D E EE4 all 26 Slide 22

12 2 Logic unctions, Symbols, & Notation TRUTH NME SYMOL NOTTION TLE NOT = OR = + ND = EE4 all 26 Slide 23 Logic unctions, Symbols, & Notation 2 NOR = + NND = XOR (exclusive OR) = + EE4 all 26 Slide 24

13 3 Circuit Realization! = + = ( + ) i( + ) = i + +! EE4 all 26 Slide 25 Logic unctions, Symbols, & Notation TRUTH NME SYMOL NOTTION TLE NOT = OR = + ND = EE4 all 26 Slide 26

14 4 Logic unctions, Symbols, & Notation 2 NOR = + NND = XOR (exclusive OR) = + EE4 all 26 Slide 27 an in/an out Complex digital operations are formed with a variety of gates interconnected to yield the desired logic function. Sometimes a number of inputs are connected to one gate input and output of a gate may be connected to a number of gates. an-in: the maximum number of logic gates that can be connected at the input of a gate without altering its performance. an-out: the maximum number of logic gates that can be connected to the output of a gate without altering its performance. Typical fan-in and fan-out numbers are 3. EE4 all 26 Slide 28

15 5 Inverter = NOT Gate V in V out Ideal Transfer Characteristics V out V/2 V V in EE4 all 26 Slide 29 Terminology for a Logic Circuit V IN I OUT V DD R PULL UP Output Pull-Down (NMOS) V OUT V DD = Power supply voltage (D is from Drain) we do not draw the symbol. Pull-Up Network = Set of devices used to carry current from the power supply to the output node to charge the output node to the power supply voltage. Pull-Down Network = Set of devices used to carry current from the output node to ground to discharge the output node to ground. I OUT = Current for the device under study. V TD = Threshold Voltage value of V IN at which the Pull-Down (NMOS transistor) begins to conduct. V OUT-ST-D = Value of V OUT beyond which the current I OUT-D saturates at the (drain) current saturation value I OUT-ST-D. EE4 all 26 Slide 3

16 6 Pull-Up and Pull-Down V DD = Power supply voltage (D is from Drain) we do not draw the symbol. PMOS or Resistor NMOS or Resistor Pull-up current V logic state of Pull-down current V logic state of Non-zero V DD Some value Non-zero Some value GND EE4 all 26 Slide 3