EE241 - Spring 2002 Advanced Digital Integrated Circuits

Transcription

1 EE241 - Spring 2002 dvanced Digital Integrated Circuits Lecture 7 MOS Logic Styles nnouncements Homework #1 due 2/19 1

2 Reading Chapter 7 in the text by K. ernstein ackground material from Rabaey References» [Rabaey 95] J.M. Rabaey Digital Integrated Circuits: Design Perspective, Prentice Hall 1995.» [ernstein 98] K. ernstein et al, High-Speed CMOS Design Styles, Kluwer 1998.» [Oklobdzija99] V.G. Oklobdzija, High- Performance Systems: Circuits and Logic, IEEE Press CMOS Logic Styles CMOS tradeoffs:» Speed» Power (energy)» rea Design tradeoffs» Robustness, scalability» Design time Many styles: don t try to remember the names remember the principles 2

3 CMOS Logic Styles Complementary VDD Pass Transistor Logic C PUN OUT C LOGIC NETWORK OUT C PDN GND robust scales simple and fast not always very efficient versatile large and slow CMOS Logic Styles Ratioed Logic VDD Dynamic Logic LOD φ Out GND C PDN OUT R PDN << R LOD In 1 In 2 In 3 PDN C L φ GND small & fast static power Small & fastest! Noise issues Scales? 3

4 Static CMOS Complementary CMOS In1 In2 In3 PUN PMOS Only F = G In 1 In 2 In 3 PDN NMOS Only V SS Complementary CMOS Very robust, full swing, high noise margins Fast to design, can synthesize No static power mong other properties:» Different pull-up and pull-down delays» Delay dependence on history» Crowbar current» Input capacitance consists of both P and N» Fast NND, NOR, slow MUX, XOR 4

5 Complementary CMOS Courtesy of IEEE Press, New York Transfer Function and Noise Margin Courtesy of IEEE Press, New York

6 Propagation Delays t plh t phl t p VTC of Complementary CMOS Gates M 3 M 4 F M 2 int M 1 6

7 Delay Dependence on Inputs R P R P 3.0 = = 1 0 R N F C L = 1, = 1 0 = 1 0, =1 R N C int time, ps ody Effect 7

8 Pulsed Static CMOS RH Reset high RL Reset low Fast pull-up Fast pull-down Chen, Ditlow, US Pat. 5,495,188 Feb PS-CMOS Evaluation and reset waves: reset is 1.5x slower 8

9 dvantages: PS-CMOS» No dynamic nodes good noise immunity» Reset delay slower than evaluation» No data dependent delay (worst case gets better)» No false transitions Disadvantages» Width of reset wave limits logic depth» Margin in design Skewing Gates Different rising and falling delays W W LE = 9

10 Skewing Gates 4W W LE = Skewing Gates 10

11 Ratioed Logic Resistive Load R L F Depletion Load V T < 0 F PMOS Load V SS F In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN In 1 In 2 In 3 PDN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudo-nmos Goal: to reduce the number of devices over complementary CMOS Pseudo-NMOS PMOS load 2.0 W/L p = 4 F 1.5 In 1 In 2 In 3 PDN V, t V ou W/L p = 0.5 W/L p =.25 W/L p = 1 W/L p = V in, V 11

12 Differential Logic Differential Logic Differential Cascode Voltage Switch (DCVS) Differential Split-Level (DSL) Cascode Non-Threshold Logic (CNTL) Regenerative Push-Pull Cascode Logic (PPCL) Pass transistor logic families Dynamic logic families 12

13 Differential Logic Cascode Voltage Switch Logic M1 M2 Out Out PDN1 PDN2 V SS V SS Cascode Voltage Switch Logic (CVSL) Sometimes called Differential Cascode Voltage Switch Logic (DCVSL) 13

14 CVSL - V th Out M 1 Out M 3 M 4 Voltage,V ,, Out Out M Time, ns Fast No static power dissipation CVSL Full adder design How to design for reduced transistor count? 14

15 Karnaugh Map Technique Karnaugh Map Technique x 2 x x LOD LOD uild shared cubes first! x 1 Q Q x 1 x 1 x 1 Q Q x 1 x 2 x 2 x 2 x 2 x 2 dd other cubes next x 3 x 3 x 3 x 3 15

16 Example Q = x 1 x 2 x 3 x 4 + x 1 (x 2 +x 3 +x 4 ) Using Ordered DDs DD = inary Decision Diagrams 16

17 Push-Pull Cascode Logic Gieseke et al, U.S. Patent 5,023,480 June DSL Differential Split-Level Logic 17

18 Simulation Results for Different dders 18