Lecture 27: MOSFET Circuits at DC.
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1 Whites, EE 30 Lecture 7 Page 1 of 8 Lecture 7: MOSFET Circuits at C. We will illustrate the C analysis of MOSFET circuits through a number of examples in this lecture. Example N7.1 (similar to text Example 5.3). esign the circuit below so that the MOSFET operates with I 0.4 ma and V 1 V. The MOSFET has Vt V, ncox 0 A/V, L 10 m, and W 400 m. Neglect the channel-length modulation effect ( 0). I 0.4 ma V 1 V This last statement (i.e., = 0) means we can neglect the MOSFET ouut resistance ( r o ). R ma 10 k 017 Keith W. Whites
2 Whites, EE 30 Lecture 7 Page of 8 From this circuit we can see that VG 1 V, which is less than V t. Consequently, the channel is pinched off at the drain end. Therefore, the MOSFET is operating in the saturation or cutoff modes (not the triode) depending on the resulting value for V S. We ll assume operation in the saturation mode. In this mode 1 W 1 W I k n V Vt ncox V Vt L L Substituting 1 6 A ma 010 V V 10 Therefore V 1 V 1 or V 1 V or 3 V The first solution is not consistent with our initial assumption of operation in the saturation mode since it is less than V t. Therefore, V 3 V V 3 V S Finally, R S VS 5 VS 5 35 I I 0.4 ma 5 k S Example N7. (similar to text Exercise 5.9). esign the circuit below so I = 0.4 ma. The MOSFET has Vt V, C 0 A/V, L 10 m, and W 100 m. Neglect r o. n ox
3 Whites, EE 30 Lecture 7 Page 3 of 8 V With the gate and drain terminals connected together VG 0, which is not greater than V t. This means the channel is not continuous and the MOSFET is not operating in the triode mode. We ll assume the device is operating in the saturation mode. In saturation, 1 W I ncox V Vt L 1 or V V 10 Consequently, V 0 or 4 V The first solution is not consistent with operation in the saturation mode since V Vt. Hence, with V 4 V and VG 0 V V 4 V. Finally, since IG 0 then 10 V 10 4 R k 15 kω 0.4 ma 0.4
4 Whites, EE 30 Lecture 7 Page 4 of 8 Example N7.3 (text Example 5.4). esign the circuit below for a drain voltage of 0.1 V. etermine r S. The MOSFET has Vt 1 V and k W L 1 ma/v. Neglect r o. n (Fig. 5.3) With V 5 V and greater than V t, the MOSFET has an induced channel and is not cutoff. Next, let s check to see if the channel is pinched off at the drain end. We can do this two (equivalent) ways. First, with V 0.1 V then VG V which is greater than V t (= 1 V), so the channel is not pinched off at the drain. Alternatively, we can compute V Vt 51 4 V which is greater than V S (= 0.1 V). So again we find that the channel is not pinched off at the drain. Either of these two results means the MOSFET is operating in the triode mode (continuous channel).
5 Whites, EE 30 Lecture 7 Page 5 of 8 In the triode region, W 1 I k n V Vt VS VS L (5 1)0.1 (0.1) so that I ma Then and R r S k 1.41 kω VS 0.1 k 53 Ω I We could also use (5.13) for this last result, but the work was already done here. From the text, Using the values above, v W r k V V S S n t i vs small L v V (5.13b) r S. This value is slightly different than what was calculated earlier. Which one is correct? Why is the other not as accurate? Example N7.4 (text Example 5.7). esign the circuit below so that the MOSFET is operating in the saturation mode with I 0.5 ma and V 3 V. What is the largest R such that the
6 Whites, EE 30 Lecture 7 Page 6 of 8 MOSFET remains in the saturation mode? The MOSFET has V 1 V and k W L 1 ma/v. Neglect r o. p (Fig. 5.5) The drain resistor can be determined from the circuit above 3 R k 6 kω 0.5 Saturation mode in an enhancement type PMOS device requires V V (induced) or VSG V (induced) (1) and VS V V (pinched off) () In words, this last equation states that the drain-to-source voltage must be less than the gate-to-source voltage plus V. When working with PMOS transistors, the negative V and other minus signs can sometimes cause confusion. So we can use V SG in (1) for determining the presence of an induced channel, and can multiply () for a pinched off channel at the drain end (saturation mode) by -1
7 Whites, EE 30 Lecture 7 Page 7 of 8 VS V V and rearrange to read VS V V VSG V (pinched off) (3) where V OV p V V V (4) OV p SG Equation (4) is only valid for a PMOS transistor that has an induced channel [such that the RHS of (4) is a positive number, as defined by the LHS]. Now, in the saturation mode (with 0) I 1 W 1 k V V k L L V V 1 W k p VSG V L or V 1 Therefore, V 1 1 V 0 or - V. W 1 p p (5.8),(5) The first result is not consistent with operation in the saturation mode since V V must be met for saturation. Consequently, V 5V 5 3 V G R G1 and R G must be chosen such that RG 3 RG VG VS or R R 5 R R G1 G G1 G
8 Whites, EE 30 Lecture 7 Page 8 of 8 The text chooses RG1 M and RG 3 M to satisfy this requirement. (Why did the book use such large values for R G1 and R G?) For the largest R, remember that the PMOS device remains in the saturation mode as long as the drain end of the channel is pinched off. V SG V V G V S G Channel pinch off at the drain end requires V V (pinched off) G which holds up to the point where V exceeds V G by V is, V V V 31 4 V. From this result, R G max V 4 V 0.5 ma max 8 k. max I. That
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