Power Optimization of FPGA Interconnect Via Circuit and CAD Techniques

Transcription

1 Power Optimization of FPGA Interconnect Via Circuit and CAD Techniques Safeen Huda and Jason Anderson International Symposium on Physical Design Santa Rosa, CA, April 6,

2 Motivation FPGA power increasingly critical because of new markets Data centers Mobile electronics *Google data centre 2

3 Motivation FPGAs typically have underutilized wires We ask: Can we take advantage of unused wires? This work: 3 techniques to reduce power w/ unused wires Charge recycling (dynamic) Effective capacitance reduction (dynamic) Pulse-based signalling (static) 3

4 Dynamic Power Reduction Techniques 4

5 Motivation *Figure taken from [Tuan07] Routing power is prime component of FPGA dynamic power 5

6 Charge Recycling in FPGA Interconnect 6

7 Dynamic Power in Conv. CCTs V DD V DD C L V DD coulombs of charge drawn from supply 0 CL V DD CL Switching from 0 to 1 draws C L V DD 2 joules 7

8 Dynamic Power in Conv. CCTs V DD V DD V DDCL 0 C L C L V DD coulombs of charge dissipated All of the stored energy in C L is dissipated Can we use the energy that is being dissipated? 8

9 Charge Recycling (CR) Concept V DD Initial Phase V DD 0 C L C R During 1 0 transition, output starts at V DD PDN disconnected, PUN connected 9

10 Charge Recycling (CR) Concept Charge Recovery Phase V DD *Assume C L = C R V DD /2 V DD /2 C L C R PUN, PDN disconnected, C L connected to C R ½ C L V DD coulombs of charge transferred 10

11 Charge Recycling (CR) Concept V DD Final Phase 0 V DD /2 C L C R PDN connected, PUN disconnected Output pulled to GND, ½ C L V DD coulombs dissipated 11

12 Charge Recycling (CR) Concept V DD Initial Phase 0 V DD /2 C L C R Output initially at GND during a 0 1 transition ½ C L V DD coulombs stored in C R 12

13 Charge Recycling (CR) Concept Charge Recycling Phase V DD *Assume C L = C R V DD /4 V DD /4 C L C R PUN, PDN disconnected, C L connected to C R ¼ C L V DD coulombs of charge transferred to C L 13

14 Charge Recycling (CR) Concept V DD Final Phase V DD V DD /4 C L C R ¾C L V DD coulombs of charge drawn from supply Implies 25% reduction in energy consumption 14

15 Observations We can reduce power if reservoir capacitors are available Use unused wires as reservoirs! CR requires complex set of steps -- area penalty to implement? FPGA routing circuits are big to begin with Large routing multiplexers Several SRAM cells Large output buffers to drive long capacitive wires Incremental area overhead of complex circuitry may not be too bad 15

16 CR in FPGAs Designs on FPGAs typically have paths with lots of slack Can trade-off the delay of these paths for power savings using CR Opportunity: [Anderson09] showed that 75% of switches in a design can be slowed down by 50% Target CR in FPGA routing switches Routing Switch Target output buffer for charge recovery/recycling Inputs V IN V IN Routing Wire ` 16

17 Proposed FPGA Routing Arch. CLB CLB CR Buffer SB Friend Conductors (2 way sharing) CLB CLB 17

18 CR Routing Buffer V DD CR TS V DD CR TS M10 V IN Gating Circuitry M9 C Wire Delay Line CR CR D IN DIN CR CR TS TS V IN_D CR Circuit Unused Routing Conductor SRAM Cell SRAM Cell C Wire C R = C WIRE CR sets state of buffer CR mode vs. Normal mode TS sets one of two friend buffers in tristate mode 18

19 Functional Simulation Output Recovery Phase Node Voltage [V] Reservoir Recycling Phase Time [ns] Simulated in ST65 process Approx. 26% power reduction Theoretical reduction of 33% - circuit overheads Assuming 200fF interconnect load 19

20 CAD Tool Support Power can be reduced for a routing switch if: 1) Friend conductor is unoccupied 2) Switch lies along path with sufficient slack To optimize CR in FPGAs, we need CAD which: Maximizes the availability of free reservoirs for nets with high activity and sufficient slack Optimizes the mode selection of switches 20

21 CAD Flow CIRCUIT Conven&onal VPR 6.0 packing and placement Modified VPR 6.0 Router Op&mizes availability of free reservoirs Post- rou&ng phase to select opera&ng mode of switches (CR vs. Normal) Packing Placement CR- aware Router Switch Mode Selection Net Activities %CR Capable Switches Timing Constraint.net,.route,.place files f max, power estimate 21

22 Results!"#$%&'$( )*+,&-$+-.*$( 5678(9'+*$"#$(&'( 0*&:+"%(;"-,( )*+,&-$+-.*$( (/&-,(01(0"2"3&%&-4( Arch. with 100% CR capable switches Best case 1.3% degradation CP delay Due to increased delay of CR capable switches Extra ~3% power reduction as delay constraints relaxed 22

23 Effective Interconnect Capacitance Reduction 25

24 VLSI Wire Capacitance M5 M4 C P C P C C C C C P C C C P C C C P C C C P C C C P C P C P C P C P M3 Wire capacitance consists of: Coupling capacitance (C C ) between adjacent wires on same layer Plate capacitance (C P ) between adjacent wires on different layers Due to aspect ratio of wires, C C is dominant 28

25 Wire Capacitance Optimization in ASICs (1) s 1 Total channel width, W net i net j net k w 1 s 2 w 2 s 3 w 3 s 4 In ASICs, have freedom to optimize wire width and spacing Can optimize w i and s i to maximize timing, minimize power Optimize w i and s i subject to Σw i + Σs i = W 30

26 Wire Capacitance Optimization in ASICs (2) Total channel width, W net i net j net k w 1 s 2 w 2 s 3 w 3 If net j is timing/power critical: Can increase s 2 and s 3 to reduce C C Reduces capacitance on net j, improves speed and reduces power Can also optimize w 1, w 2, w 3 for speed and power 31

27 In FPGAs? Routing Option 1 Routing Option 2 USED Conductors net i net j net k UNUSED Conductors USED Conductors net i net j net k UNUSED Conductors FPGA wiring prefabricated, width and spacing fixed Can t space used wires apart, unused wires in the way Capacitance on wires in two routing options the same Despite the fact that nets i,j,k are now spaced further apart 32

28 Wire Cap. Optimization (1) C C2 C C1 = C C C C1 C P Routing Conductor 2 C P Routing Conductor 3 IN 2 Z IN (s) C C2 + C P R EQ C P IN 1 Routing Conductor 1 What s the total impedance seen by Routing Conductor 1, looking towards Routing Conductor 2? 33

29 Wire Cap. Optimization (2) C C1 = C C C C1 = C C Z IN (s) Z IN (s) C C2 + C P R EQ C C2 + C P R EQ If R eq is small, capacitor C C2 + C P is shorted out Impedance looking towards Routing Conductor 2 is the capacitor C c 34

30 Wire Cap. Optimization (3) C C1 = C C C C1 = C C Z IN (s) Z IN (s) C C2 + C P R EQ C C2 + C P R EQ If R eq is large, we approximate as an open circuit Z IN equal to series combination of C C and C C2 + C P 35

31 Wire Cap. Optimization (3) Series combinations of capacitors result in reduced capacitance: If C 1 in series with C 2, eq. capacitance C eq = C 1 C 2 /(C 1 + C 2 ) < C1 Therefore can reduce capacitance if R eq is large enough Making R eq large is bad buffer delay ~ R eq C wire --> increase in R eq increases delay What if we made R eq large only for unused conductors? Would not result in increased delay of used conductors Neighbouring used conductors would see benefit of reduced cap. Need to be able to set R eq large for unused conductors, but small for used conductors Used tri-state buffers! 36

32 This Work USED Conductors net i net j Tristated Tristated Nets i and j still see reduced coupling capacitance UNUSED Conductors net k If intermediate wires are tristated, see reduced C C!! In this work we tristate unused wires to reduce wire cap Proposed a novel, lightweight TSB topology Used similar CAD techniques to CR work (won t cover in this talk) 40

33 Proposed Tristate Buffer 41

34 Traditional Tri-state Buffers V DD TS M5 V DD M3 M2 M4 IN OUT M1 M6 Header transistor M5 cuts off pull up path to output Unused buffer would have IN at VDD M 1 pulls gate of M 6 to GND Large area cost: M 2, M 4 and M 5 must be big due to of stacking 42

35 Optimized Headerless TSB V DD V DD V DD M2 M7 TS V DD V DD M9 IN M3 M5 M4 TS M8 OUT M1 No stacking in output stage Leverages fact that unused buffers have their input pulled high (details in paper) 43

36 CAD Flow CIRCUIT Conven&onal VPR 6.0 packing and placement Modified VPR 6.0 Router Op&mizes rou&ng to reduce capacitance of nets Packing Placement Wire Cap Opt. Router Net Activities C C /C P.net,.route,.place files f max, power estimate Power and speed of a conductor can be optimized if adjacent conductor(s) unused; similar to CAD flow in CR project User supplied C C /C P to estimate cap. reduction 46

37 Results!"#$%&'""$&#()'*$%(+$,-&.'"( ('"# (&"# (%"# ($"# (!"# '"# &"# %"# $"#!"# (# ()$# ()%# ()&# ()'# $# $)$# $)%# $)&# $)'# *# / / 0/ )( Dynamic power reduction exceeds 15% for C C /C P 3 Get additional 14.6% leakage power savings from TSB Critical path degradation ~1% Total area overhead ~2.1% 48

38 Static Power Reduction in FPGA Interconnect 50

39 Routing Leakage Sources V DD VDD M 4 M 2 M 3 M 1 S S S S V SS Leakage path between rails of config. memory Can be minimized by using HVT xtors. 51

40 Routing Leakage Sources V DD VDD M 4 M 2 M 3 M 1 S S S S V SS Leakage path between rails of routing buffer 52

41 Routing Leakage Sources V DD VDD M 4 M 2 M 3 M 1 S S S S V SS Leakage paths between different inputs of routing mux Modern archs. have large muxes à many leakage paths 53

42 This Work Can we shut off routing circuits when not active? i.e. not in the process of transmitting data Effectively a very aggressive form of power gating Dominant leakage paths in the routing network begin and end at routing buffers Leakage between rails of routing buffer Leakage between inputs pins of routing muxes originate and terminate at outputs of buffers driving these input pins Therefore, only shut off routing buffers when not transmitting data We call this pulsed-signalling 54

43 This work Recall CR operation: Output buffer is tristated immediately following input transition Wait (while charge is transferred b/w load and reservoir) Output buffer is activated after transfer of charge Pulsed-signalling is the exact opposite Output buffer is activated immediately following input transition Wait (for transition to be reliably detected by downstream circuits) Output buffer is tristated after signal transition Therefore we can use similar circuits as CR work to significantly reduce static power! Similar area overhead 55

44 Low Leakage Buffer Design V DD Coupling Cap. (MIM Cap) M 7 VINB M 9 M 10 V IN C C Receiver Stage Gating Stage V OUT M 11 Routing multiplexor M 8 V INB M 12 Routing conductor Main Buffer Stage Low Leakage Diodes act as keepers Main buffer is active for a period of time (Δt seconds) after transition appears at input Main buffer is tristated Δt seconds after transition 56

45 Low Leakage Buffer Design V DD Coupling Cap. (MIM Cap) M 7 VINB M 9 M 10 V IN C C Receiver Stage Gating Stage V OUT M 11 Routing multiplexor M 8 V INB M 12 Routing conductor Main Buffer Stage In quiescent state voltage of routing wire may drift Due primarily to leakage Excessive voltage drift can lead to errors Magnitude of drift controlled by diodes Low Leakage Diodes act as keepers 57

46 Low Leakage Buffer Design V DD Coupling Cap. (MIM Cap) M 7 VINB M 9 M 10 V IN C C Receiver Stage Gating Stage V OUT M 11 Routing multiplexor M 8 V INB M 12 Routing conductor Main Buffer Stage Low Leakage Diodes act as keepers Non- digital voltage levels may lead to issues in downstream circuits Use capacitive coupling to DC voltage of routing wire from downstream circuits (MIM cap. used as coupling cap) Full latch used as receiver 58

47 Potential Pitfalls? V DD V DD Active Routing Driver V DD V DD V CPL V DTB Tristated Routing Driver Need to ensure V DTB is less than the switching threshold of downstream latch to prevent crosstalk-induced errors Only operate buffers in this mode of operation if a sufficient number of neighbours are unused 64

48 Robust Operation of Dynamic Gated Buffer Guarantee robust operation of buffer by ensuring certain number of adjacent wires are unused These act as shields Assume noise on routing wires is dominated by wire-towire coupling Assume layers above and below routing wires can adequately shield wires from noise sources above/below ALL noise comes from adjacent wires 65

49 CAD Tool Support Denote w.c. coupling noise on routing conductor N MAX (i) N MAX (i) is the sum of coupling noise from all neighbours Each neighbour contributes (C C /C T )V DD volts of noise C C is the coupling cap. between neighbours, C T is total cap. Let N S = max. noise s.t. receiver can suppress Receiver must be able to distinguish b/w noise and data When circuit is subject to 6σ parameter variation Static power redux possible if N MAX N S CAD support must: Route design to maximize # of conductors with N MAX N S Try to ensure conductors neighbouring used conductors are unused Optimizes the mode selection of switches 66

50 CAD Flow CIRCUIT Conven&onal VPR 6.0 packing and placement Packing Placement Modified VPR 6.0 Router Op&mizes # of rou&ng conductors with N MAX N S Post- rou&ng phase to select opera&ng mode of switches (PS vs. Normal) PS- aware Router Mode Selection C C /C P (Indicates magnitude of coupling noise).net,.route,.place files f max, power estimate 67

51 Methodology Assessed power savings with a combination of MCNC and VTR benchmark circuits Routed circuits at 1.3 x W MIN and W MAX W MAX is which is 1.1x largest W MIN in benchmark set Setting W = W MAX may be more realistic 69

52 Results (W = 1.3 x W MIN ) Power Reduction[%] Active Leakage Reduction Total Leakage Reduction 25% geomean active leakage reduction 30% geomean total leakage reduction 70

53 Results (W = W MAX ) Power Reduction[%] Active Leakage Reduction Total Leakage Reduction At W MAX number of routing conductors with unoccupied neighbours increases Increases active leakage reduction Total leakage redux increase less pronounced 71

54 Conclusions Interconnect is the prime culprit in FPGA power Presented three approaches to reduce power in FPGA interconnect, all which leverage unused interconnect resources: Charge recycling Coupling capacitance reduction Pulse-based signalling First two approaches target dynamic power; third approach targets leakage power. Future work: assess power benefits when multiple techniques are combined 72

55 Questions? 73