Very Large Scale Integration (VLSI)

Transcription

1 Very Large Scale Integration (VLSI) Lecture 6 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI 1

2 Contents Array subsystems Gate arrays technology Sea-of-gates Standard cell Macrocell Technology FPGA Technology Dr. Ahmed H. Madian-VLSI 2

3 Gate Arrays and Sea-of-Gates This means to construct a common base array of transistors and personalize the chip by altering the metallization (metal and via masks) that is placed on top of the transistors. Dr. Ahmed H. Madian-VLSI 3

4 Gate Arrays Technology prefabricated wafers I/O stages predefined regular array of fets and interconnection channels interconnection defines functionality features size: 100-1M gates short turn around time cheap at medium quantities Unsuitable for regular structures like RAM, PLA, ALU Dr. Ahmed H. Madian-VLSI 4

5 Gate Array Sea-of-gates polysilicon V DD rows of uncommitted cells GND metal possible contact Uncommited Cell In1 In2 In3 In4 routing channel Committed Cell (4-input NOR) Out Dr. Ahmed H. Madian-VLSI 5

6 Sea-of-Gate Technology prefabricated wafers I/O stages predefined regular array of fets, no reserved interconnection channels interconnection defines functionality features size: 100-1M gates short turn around time cheap at medium quantities suitable for regular structures like RAM, PLA, ALU Dr. Ahmed H. Madian-VLSI 6

7 Standard Cell Technology complete fabrication process predefined library of base functions modular similar to TTL families features chip size limits complexity cheap at high quantities standardized cell height unsuitable for regular structures more flexible and compact than gate array Dr. Ahmed H. Madian-VLSI 7

8 Standard cell layout Layout made of small cells: gates, flipflops, etc. Cells are hand-designed. Assembly of cells is automatic: cells arranged in rows; wires routed between (and through) cells. Dr. Ahmed H. Madian-VLSI 8

9 Guidelines to Creating a Standard Cell Library Vertical and Horizontal Routing Grids: - Cell pins, with the exception of abutment pins (VDD and GND) must be placed on the intersections of the vertical and horizontal routing grids. - Vertical and horizontal routing grids may be offset with respect to the cell s origin, provided that the offset distance is exactly one-half of the grid spacing. - The cell height must be a multiple of the horizontal grid spacing; the cell width must be a multiple of the vertical grid spacing. Dr. Ahmed H. Madian-VLSI 9

10 (a) Without Offset Horizontal Grid Spacing (b) With Offset One-half Horizontal Grid Spacing Horizontal Grid Spacing One-half Horizontal Grid Spacing Cell Origin Figure 1: Horizontal Routing Grid Examples Dr. Ahmed H. Madian-VLSI 10

11 (a) Without Offset (b) With Offset Cell Origin Vertical Grid Spacing One-Half Vertical Grid Spacing Figure 2: Vertical Routing Grid Examples Dr. Ahmed H. Madian-VLSI 11

12 (a) Without Offsets (b) With Vertical and Horizontal Offsets Figure 3: Sample Standard Cell Routing Grid Dr. Ahmed H. Madian-VLSI 12

13 Feedthrough area Standard cell structure VDD pin pullups n tub pulldowns Intra-cell wiring p tub VSS pin Dr. Ahmed H. Madian-VLSI 13

14 Standard cell design Pitch: height of cell. All cells have same pitch, may have different widths. VDD, VSS connections are designed to run through cells. A feedthrough area may allow wires to be routed over the cell. Dr. Ahmed H. Madian-VLSI 14

15 Cell Design Standard Cells General purpose logic Can be synthesized Same height, varying width Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell Fixed height and width Dr. Ahmed H. Madian-VLSI 15

16 What are Routing Grids For? The routing grids are where the over-the-cell metal routing will be routed. The pins of your standard cells should always lie on the intersections of the horizontal and vertical routing grids. Although some CAD tools will route to off-grid pins, this may cause some other complications. Dr. Ahmed H. Madian-VLSI 16

17 Single-row layout design cell cell cell cell cell Routing wire channel Horizontal track Vertical track height cell cell cell cell cell Dr. Ahmed H. Madian-VLSI 17

18 Routing channels Tracks form a grid for routing. Spacing between tracks is center-to-center distance between wires. Track spacing depends on wire layer used. Different layers are (generally) used for horizontal and vertical wires. Horizontal and vertical can be routed relatively independently. Dr. Ahmed H. Madian-VLSI 18

19 Routing channel design Placement of cells determines placement of pins. Pin placement determines difficulty of routing problem. Density: lower bound on number of horizontal tracks needed to route the channel. Maximum number of nets crossing from one end of channel to the other. Dr. Ahmed H. Madian-VLSI 19

20 Pin placement and routing Density = 3 Density = 2 a b c a b c b c a a c b before before Dr. Ahmed H. Madian-VLSI 20

21 Example: full adder layout Two outputs: sum, carry. x1 n1 n2 n4 sum x2 n3 carry Dr. Ahmed H. Madian-VLSI 21

22 Layout methodology Generate candidates, evaluate area and speed. Can improve candidate without starting from scratch. To generate a candidate: place gates in a row; draw wires between gates and primary inputs/outputs; measure channel density. Dr. Ahmed H. Madian-VLSI 22

23 A candidate layout a Density = 5 b x1 x2 n1 n2 n3 n4 s c cout Dr. Ahmed H. Madian-VLSI 23

24 Improvement strategies Swap pairs of gates. Doesn t help here. Exchange larger groups of cells. Swapping order of sum and carry groups doesn t help either. This seems to be the placement that gives the lowest channel density. Cell sizes are fixed, so channel height determines area. Dr. Ahmed H. Madian-VLSI 24

25 Left-edge algorithm Basic channel routing algorithm. Assumes one horizontal segment per net. Sweep pins from left to right: assign horizontal segment to lowest available track. Dr. Ahmed H. Madian-VLSI 25

26 Example A B B C A B C Dr. Ahmed H. Madian-VLSI 26

27 Limitations of left-edge algorithm Some combinations of nets require more than one horizontal segment per net. A B? B aligned A Dr. Ahmed H. Madian-VLSI 27

28 Vertical constraints Aligned pins form vertical constraints. Wire to lower pin must be on lower track; wire to upper pin must be above lower pin s wire. A B B A Dr. Ahmed H. Madian-VLSI 28

29 Dogleg wire A dogleg wire has more than one horizontal segment. A B B A Dr. Ahmed H. Madian-VLSI 29

30 Rat s nest plot Can be used to judge placement before final routing. Dr. Ahmed H. Madian-VLSI 30

31 Guidelines to Creating a Standard Cell Library A standard cell library must contain at least the following cells to be able to implement any function: - NAND - NOR - NOT - DFF Additionally, you can expand the standard cell library to include additional cells like Tie-high, Tie-low cells, I/O Pads, and multiple-input gates (e.g. a 4-input NOR gate). Dr. Ahmed H. Madian-VLSI 31

32 Standard Cells N Well V DD Cell height 12 metal tracks Metal track is approx Pitch = repetitive distance between objects Cell height is 12 pitch 2 In Out Cell boundary GND Rails ~10 Dr. Ahmed H. Madian-VLSI 33

33 Multi-Fingered Transistors One finger Two fingers (folded) Less diffusion capacitance 34 Dr. Ahmed H. Madian-VLSI

34 Standard cell Dr. Ahmed H. Madian-VLSI 35

35 Datapath Layout Example: Adder Standard cell layout Bit-slice cell layout Dr. Ahmed H. Madian-VLSI 36

36 Arithmetic and Logic Unit (ALU) Functions Arithmetic (add, sub, inc, dec) Logic (and, or, not, xor) Comparison (<, >, <=, >=,!=) Control signals Function selection Operation mode (signed, unsigned) Output Operation result (data) Flags (overflow, zero, negative) Dr. Ahmed H. Madian-VLSI 37

37 Architecture of a CPU Control Flags: overflow, zero, etc. Read/write Mem Register File Data path Dr. Ahmed H. Madian-VLSI 38

38 Data in Register Adder Shifter Multiplexer Data Out Simple ALU Example Control Bit 3 Bit 2 Bit 1 Bit 0 Tile identical processing elements [ Prentice Hall] Dr. Ahmed H. Madian-VLSI 39

39 Macrocell Technology complete fabrication process combines semi- and full custom technologies predefined library of base functions generators for regular structures features chip size limits complexity short design, long fabrication time cheap at high quantities high flexibility, compact layouts Dr. Ahmed H. Madian-VLSI 40

40 Full Custom Technology complete fabrication process total flexibility, only limited by layout rules manual design features chip size limits complexity long design and fabrication time efficient use of silicon area cheap only at highest quantities (ex. up, memories,...) Dr. Ahmed H. Madian-VLSI 41