A COMPARATIVE ANALYSIS OF 180 NM PROCESS CMOS INVERTER

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1 A COMPARATIVE ANALYSIS OF 180 NM PROCESS CMOS INVERTER Amresh Kumar Lenka Department of Electronics and Communication Engineering Centre for Advance Post Graduate Studies, Rourkela Ananya Dastidar Biju Patnaik University of Technology, Odisha, India Abstract In this paper an analysis of the CMOS Inverter has been carried out using Cadence Virtuoso Generic Process Design kit 180. The inverter is tested with load and no load conditions at both 25oC and 125oC. The proposed inverter is tested for power consumption along with noise margin and average propagation delay. The result of the noise margin and average propagation delay analysis is compared with 0.3uM bulk driven inverter. Keywords Inverter threshold voltage; threshold voltage; propagation delay; noise margin; generic process design kit 180. I. INTRODUCTION The CMOS inverter is the most common digital component used in today s electronics [1-4] and it is almost impossible to implement any complex logic without the use of an inverter, hence making it one of the most important digital component. The function of the inverter is to invert the logic at its input end. So how well the logical inversion is occurring in different loads and environmental conditions is a very important information to be analyzed. In order to know the operational range of our electronic circuit, this analysis has been performed. Cadence Virtuoso a Linux based PSpice like program, used to create and analyze the CMOS inverter. The NMOS and PMOS used to develop the proposed Inverter was considered from the gpdk180 library of Cadence Virtuoso. Gpdk180 of Cadence is a generic process design kit in which the least gate length of a transistor can be 180nm and this process design kit provides necessary rules to make digital and analog designs [6]. II. CMOS INVERTER CMOS inverter can be implemented using one NMOS and one PMOS transistor connected in series with each other, each behaving as load and driver. The most important advantages of CMOS inverter are sharp VTC and almost negligible steady state power consumption [1].Both NMOS and PMOS will act as load and driver. The major power consumption in the CMOS inverter occurs during logical inversion, and the point of peak power consumption usually present at the inverter threshold voltage point of VTC curve, Hence making the inverter threshold voltage a critical voltage to be analyzed. Equation of inverter threshold voltage also gives the relationship to design a symmetric inverter. A. VOLTAGE TRANSFER CHARACTERSTICS 60

decrease in the output voltage is not abrupt and will take some finite time, the slop obtained due to this will provide the critical voltages that are required for calculation of noise margin.

2 decrease in the output voltage is not abrupt and will take some finite time, the slop obtained due to this will provide the critical voltages that are required for calculation of noise margin. Figure 1: Proposed Inverter with different transistor voltages using cadence virtuoso gpdk180 The inverter circuit is shown with bias, here VIN is the input voltage, VOUT is the output voltage and VDD is the power supply. ID, P and ID, N are the drain current of PMOS and NMOS respectively. VGS, P and VGS, N are gate to source voltages of PMOS and NMOS respectively. VDS, N and VDS, P are drain to source voltages of NMOS and PMOS respectively. In the above device there will be no substrate bias effect as body is kept at same potential with respect to source for PMOS and NMOS. So VIN=VGS,N (1) VOUT=VDS,N (2) VGS,P= (VDD VIN (3) VDS,P= (VDD VOUT) (4) The logical inversion in inverter can be analyzed by plotting the output voltage VOUT as a function of VIN, the resultant plot will be the VTC of the inverter [1].Let assume that a DC voltage is applied at the input of the inverter, so as the input voltage increases the output voltage of inverter decreases but the Figure.2. Typical VTC of realistic CMOS inverter [1] Where VIL is input low voltage, VIH is input high voltage, VTH is inverter threshold voltage, VOH is output high voltage and VOL is output low voltage Here 3 critical voltage points can be identified from the VTC i.e. VIL VTH VIH, at two critical points VIL and VIH the slop of the VTC becomes equal to -1 i.e.[1] B. NOISE MARGIN The digital circuit is prone to noise and the noise tolerance for the digital circuit is called noise margin which is denoted by NM [1]. The noise immunity increases with NM [1]. The noise margin can be defined for low and high signal levels, the noise margin for low signal levels is defined as [1] NML=VIL VOL (5) Noise margin for high signal levels is defined as [1] NMH=VOH VIH C. CMOS INVERTER DESIGN The inverter threshold voltage VTH is defined as VTH = VIN = VOUT [1] so at this condition both the 61

transistor will be at saturation mode, from the figure 1 it can be seen that ID,N = ID,P (7) Hence substituting current equations of transistors at saturation mode [1] in equation 7 Where μn and μp

3 transistor will be at saturation mode, from the figure 1 it can be seen that ID,N = ID,P (7) Hence substituting current equations of transistors at saturation mode [1] in equation 7 Where μn and μp are the mobility of N-type and P- type respectively [1] Where VTO, N and VTO, P are zero-bias threshold voltage, Kn and KP are transconductance parameters of NMOS and PMOS respectively. Substituting VGS, N and VGS, P with equation 3 and 4 yields True solution of equation 9 is [1] So inverter threshold voltage is given by [1] Using the relationship derived in equation 15 the proposed inverter of figure 1 is designed with WP = 1uM and Wn= 400nM LP=LPN= 180nM, Width of the NMOS used is kept at 400nM because that is the minimum width possible for a transistor in GPDK180. The proposed inverter is connected to VIN = VOUT = 0.7V and the load capacitor used is an ideal capacitor from the analoglib of the cadence virtuoso, The analoglib of cadence virtuoso contains all ideal component, hence to test the proposed inverter with only capacitive load the analoglib is used. Now solving for KR yields Switching threshold voltage of ideal inverter is defined as [1] Substituting the value of VTH with equation 13 yields For completely symmetric Inverter VTO=VTO,N= VTO,P condition must satisfy So Figure.3a Inverter with a 5fF ideal load capacitor 62

Cadence Virtualization and Analysis XL and cadence ADE L is used for noise margin calculation. TABLE 1.

NOISE MARGIN OF PROPOSED INVERTER Using equation 5 and 6 noise margin can be calculated for Inverter at different load and different temperatures from table 1.

COMPARATIVE ANALYSIS OF NOISE MARGIN OF PROPOSED INVERTER WITH A 0.

4 Cadence Virtualization and Analysis XL and cadence ADE L is used for noise margin calculation. TABLE 1. COMPARATIVE ANALYSIS OF CRITICAL VOLTAGES AT DIFFERENT TEMPERATURE AND LOAD CONDITIONS Figure.3b Inverter with no load III. NOISE MARGIN OF PROPOSED INVERTER Using equation 5 and 6 noise margin can be calculated for Inverter at different load and different temperatures from table 1. TABLE 2.COMPARATIVE ANALYSIS OF NOISE MARGIN AT DIFFERENT TEMPERATURE AND LOAD CONDITIONS TABLE 3. COMPARATIVE ANALYSIS OF NOISE MARGIN OF PROPOSED INVERTER WITH A 0.35uM PROCESS BULK-DRIVEN INVERTER AT NORMAL OPERATING TEMPERATURE WITHOUT LOAD [3] Noise margin of proposed Inverter is higher and symmetric than the 0.35uM process bulk driven Inverter. IV. POWER CONSUMPTION OF PROPOSED INVERTER Net power consumption of the proposed inverter is the sum of DC and transient power. Cadence Virtualization and Analysis XL and cadence ADE L is used for power calculation. 63

5 A. DC POWER CONSUMPTION DC power is given by [1] voltage times the current of a circuit. PDC=V I TABLE 4. COMPARATIVE ANALYSIS OF NOISE MARGIN AT DIFFERENT TEMPERATURE AND LOAD CONDITIONS response of the net circuit including wires used of connection of voltages to the inverter and capacitor and the inverter is numerically same leading to the conclusion that the resistance of the external wire used by cadence virtuoso is either 0 or very small. DC power consumption of the inverter increases by 2 order of magnitude for 3 time s increase of the temperature. B. TRANSIENT POWER CONSUMPTION Transient power is given by [1] POWERTRANSIENT=COUT (VDD) 2 f (17) Where COUT is the load capacitance, VDD is the power supply, And frequency of switching is f Voltages and load used for proposed Inverter DC power supply: VDD=0.7V Square wave input: VIN=0.7V Period of square wave: P= 20nS TRISE: 10pS TFALL: 10pS Capacitor value: 5fF Transient analysis time: 20ns Net transient power is calculated by taking the average of the transient power response of proposed Inverter. The inbuilt calculator tool is used to take the average of the transient power response. As the load capacitor taken is ideal in nature so there will be no internal resistance for power to leak out. The transient Power Figure.5 Transient power response of proposed inverter TABLE 5. COMPARATIVE ANALYSIS OF AVERAGE TRANSIENT POWER CONSUMPTION AT DIFFERENT TEMPERATURE AND LOAD CONDITIONS TABLE 6. COMPARATIVE ANALYSIS OF TOTAL POWER CONSUMPTION AT DIFFERENT TEMPERATURE AND LOAD CONDITIONS 64

V. PROPAGATION DELAY Propagation delay is defined by input to output delay during the high to low τphl and low to high τplh transition of output respectively [1].

6 V. PROPAGATION DELAY Propagation delay is defined by input to output delay during the high to low τphl and low to high τplh transition of output respectively [1]. Cadence Virtualization and Analysis XL and cadence ADE L is used for propagation delay calculation. The average propagation delay τp is given by TABLE 8. COMPARATIVE ANALYSIS OF τp, τplh AND τphl FOR 0.35uM BULK DRIVEN INVERTER AND PROPOSED INVERTER AT NORMAL TEMPERATURE AND NO LOAD CONDITION [3] Figure.6 Transient response of proposed inverter for 20nS Overshoot at VOUT is due to gate-drain capacitances of the inverter transistors, which couple the steep voltage step at the input node directly to the output before the transistors can even start to react to the changes at the input. These overshoots have negative impact on the performance of the gate. [4] TABLE 7. COMPARATIVE ANALYSIS OF τp, τplh AND τphl AT DIFFERENT TEMPERATURE AND LOAD CONDITIONS VI. CONCLUSION CMOS inverter using GPDK180 has been implemented in this paper. The proposed inverter has lower propagation delay and higher noise margin than 0.35uM bulk driven inverter. At no load condition the power consumption of proposed inverter at 25oC and 125oC is almost equal, and also the average delay at 125oC is only one order of magnitude higher than 25oC, hence the proposed inverter is appropriate for high temperature and low power application. If worst case scenario is considered i.e. inverter at 125oC with 5fF load then taking the larger among the τphland τplh as the limiting factor gives a maximum of 5GHz as the safe operational speed for the inverter. Hence the proposed inverter can also be used in high speed applications. Further on using the same model relationship proposed inverter can be implemented using gpdk90 and gpdk45 for high speed RF applications. REFERENCES [1] Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, Digital Integrated Circuits a Design Perspective 2 n d edition, 1999, chap 3 [2] P. Chaourani, I. Messaris, N. Fasarakis, M. Ntogramatzi, S. Goudos, S. Nikolaidis, An Analytical Model for the CMOS Inverter, 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS),sep

7 [3] Maneesha Gupta, Bhawna Aggarwal, Priyanka Garg, Parish Aggarwal, Swati Jain, Low Voltage Bulk-Driven CMOS Inverter with Lower Delays, Annual IEEE India conference,dec.2015 [4] THE CMOS INVERTER, chap-5, sep.1999, bwrcs.eecs.berkeley.edu/classes/icdesign/ee141_f01/ Notes/chapter5.pdf [5] Using Cadence Virtuoso, a UNIX based OrCAD PSpice like program remotely on a Windows Machine, adence_virtuoso.pdf [6] y_forums/f/92/t/

Solution HW4 Dr. Parker EE477

Solution HW4 Dr. Parker EE477 Assume for the problems below that V dd = 1.8 v, V tp0 is -.7 v. and V tn0 is.7 V. V tpbodyeffect is -.9 v. and V tnbodyeffect is.9 V. Assume ß n (k n )= 219.4 W/L µ A(microamps)/V