UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences

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1 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Jan M. Rabaey Homework #1: Circuit Simulation EECS 141 Due Friday, January 29, 5pm, box in 240 Cory 1. Objective The objective of this session is to give initial exposure to the software environment that will be used in this course throughout the semester. CADENCE will be used to execute some of the procedures that are necessary in many lab and homework assignments, in addition to your project, during the course. 2. Tasks a. Make sure your account is correctly setup and that you can log in to the Linux instructional workstations located in 353 Cory Hall. Naming convention of these workstations is CORY353-xL, where x is an even number between 2 and 24. There are therefore total of 12 such workstations: CORY353-2L, CORY353-4L, CORY353-6L,, CORY353-24L. Information on how to get an instructional account (if you don t have one yet) and on how to setup CADENCE on your instructional account for EE 141 can be found under b. Setup and start CADENCE Once you logged on to one of the instructional servers create your EE141 setup by typing > /share/b/bin/cadence-linux-setup.csh You will then be asked to provide a name for the working directory (default is ee141) After the installation is done change to your working directory and start CADENCE by typing > /share/b/bin/icfb2 & If you did everything correctly an icfb Log and a Library Manager window will pop up. (Make sure you are running Exceed if you are working from a PC) c. Using the Library Manager create a working library and attach it to the 90 nm technology file > File New Library Library Name e.g.: HW1 ( ok) Attach to an existing techfile

2 Technology Library: gpdk090 d. Create a schematic view of an inverter Library Manager: > File New Cell View Make sure you chose the correct library (your working library) and specify the name of your schematic (e.g. inv) in the Create New File window popping up. The view name has to be schematic which automatically implies the Composer Schematic as tool of choice. After confirming your choice a Virtouso Schematic Editor opens and you can start designing your inverter. If you are not familiar with CADENCE you might want to take a look at one of the numerous tutorials available online (e.g. from the Worcester Polytechnic Institute or just search for tutorial cadence) and/or come to the discussions. Use the nmos1v and pmos1v from the gpdk090 library (category: Mos) and the GND and VDD symbols from the basic library (category: Supplies) for the supply connections. Keep the NMOS as minimum width and make the PMOS twice as wide and connect the bulk terminals of the NMOS and the PMOS to gnd and VDD respectively. Finally, attach an input and an output pin such that your schematic looks like in Figure 1. Figure 1: Schematic of Inverter

3 e. Create a symbol of the inverter and setup a simulation schematic. Create a symbol of the inverter by using > Design Create Cellview From Cellview in the schematic editor and edit it such that it looks like an inverter (similar to Figure 2) Figure 2: Symbol of Inverter Create another schematic view for the simulation (name it e.g. inv_sim) using the Library Manager. Next you will build an inverter chain to emulate realistic loading and simulate the delay of a single inverter. To do that start by inserting two of the inverters you just created and connect the output of the first to the input of the second. Hook up a vpulse source from the analoglib (Sources Independent) to the input of the first inverter and apply a 1 V, 500 MHz input signal through it (use 10 ps rise and fall time and add a delay of your choice to the signal). Insert a vdc source and apply a 1 V supply voltage by hooking the source up to the same VDD and gnd connectors you used when creating the schematic view of the inverter. Next, connect the inputs of 4 additional inverters to the output of the second inverter and assign names to the input and the output nets of the second inverter (e.g. In and Out). Each output of the 4 additional inverters has then to be connected to 4 more inverters. A convenient way of connecting multiple identical devices in parallel in CADENCE is to indicate multiple devices by adding <1:n> (n = 4 if you want to connect 4 devices in parallel) to the instance name of a device as shown in Figure 3. Continue by terminating the outputs of the 16 new inverters with a 2fF capacitor each (you can use capacitors from the analoglib). You can connect one capacitor to each inverter by placing one inverter and apply the same trick as described above to create multiple parallel capacitors (as long as you use the same n for both, the inverters and capacitors). When doing so you only need to draw a single wire to connect the inverters and the capacitors, the software

4 will take care of the rest. The final thing that needs to be done before you can start simulating is to add 3 inverters each terminated by a 2fF capacitor as well to the output of the first inverter. After you are done the schematic should look similar to the one in Figure 4. Figure 3: Connecting Multiple Identical Devices in Parallel

5 Figure 4: Schematic for Simulation (Inverter for which you are supposed to simulate the delay highlighted by the red ellipse) f. Simulating the Inverter Delay Open the simulator form from the schematic editor (Tools Analog Environment) and perform a transient simulation. Determine the delay from the input to the output of the second inverter (highlighted in Figure 4) at the time when the input and the output of that inverter cross 50% of their maximum values. Do that for both, falling and rising signal edges at the inverter input. Note that the waveform viewer might actually look a bit different than in a lot of tutorials you find, since we are using a newer version of cadence. However, it should not be a big problem for you to analyze your simulation using the newer tool. g. Simulating the voltage-transfer characteristic (VTC) of the inverter Next, simulate the voltage-transfer characteristic of the first inverter (the one connected to the vpulse source). This can be done by utilizing the DC simulation. (choose Analysis DC in the Analog Design Environment window) Check the dc analysis and chose

6 component parameter. Select your input pulse source as your component by clicking at the Select Component button and clicking on the input source in the schematic. A window asking which parameter you want to vary pops up and you simply choose the dc voltage, since you are interested in the behavior of the inverter for different dc input voltages. Choose 0 V to 1 V (GND to VDD) as sweep range and enable the dc simulation. Figure 5 shows the setup for the DC simulation Figure 5. Setup of DC Simulation to Simulate the Voltage-Transfer Characteristic After running the simulating you should be able to plot the voltage-transfer characteristic of the first inverter. 3. Deliverables The following has to be included in your written report: A printout of the inverter and the simulation schematic Plot of the transient response of the inverter Values for the inverter delay for falling and rising signal edges at the input Plot of the voltage-transfer characteristic of the inverter