EDA-BASED DESIGN PRACTICAL LABORATORY SESSION No. 4

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1 LABORATOIRE DE SYSTEMES MICROELECTRONIQUES EPFL STI IMM LSM ELD Station nº 11 CH-1015 Lausanne Téléphone : Fax : Site web : lsm@epfl.ch lsm.epfl.ch EDA-BASED DESIGN TP-2005/2006: EDABD2005-TP04.doc V1.0 LSM November 2005 EDA-BASED DESIGN PRACTICAL LABORATORY SESSION No. 4 First Name Family Name Date Evaluation Document Visa Evaluation Design Visa THIS REPORT MUST BE DELIVERED NO LATER THAN November 15 th, OBJECTIVES The goal of this session is to design a 1-bit full adder (FA), dimension its transistors and simulate it to meet certain specifications. As a prerequisite to building the full adder, you will need to read the following paper (can be downloaded from M. Alioto and G. Palumbo, Analysis and comparison on full adder block in submicron technology, IEEE Transactions on VLSI Systems, vol.10, No.6, December From this reference you will take the Mirror topology and size its transistors to meet the specifications detailed in this report. Essentially, these specifications assume that this full adder will be cascaded with other full adders to finally build an 8-bit adder. In TP5 you will layout the full adder, and then re-simulate the extracted circuit from the layout. On the third week (TP6) the 8-bit carry ripple adder will be built using the outcome of the previous TP's. After TP6, you will be asked to submit a report summarizing your results of TP4 through TP6. 1/7

2 2. PREREQUISITES AND READINGS Q1: (to be answered before the lab session) Based on the reference given above fill in the following table (consider the designs optimized for minimum PDP): Topology Advantages Disadvantages CMOS Full Adder Mirror Full Adder LP Full Adder 3. SCHEMATIC ENTRY Figure 3 shows the testbench used to evaluate the full adder cell. To obtain realistic input waveforms, inverters have been inserted between the ideal sources and inputs A and B, and input C i is driven by an identical FA cell in carry propagate mode (AB = 01 or 10). A 4x minimum size inverter and the C i of an identical stage load the outputs S and C O respectively. To build the testbench shown in Figure 3 proceed as follows: Draw the schematic and the symbol for the inverter used in the testbench. The transistor sizes to use are given in Figure 2. To avoid cluttered schematics, don t put pins for VDD and GND, but use the blocks vdd_inherit and gnd_inherit from library basic, as shown in Figure 2. Using these blocks allows connecting the supply of the DUT (device under test) to other nodes than the global supply nodes (vdd! and gnd!). This can be useful in a design with several different supplies; here we will use it to measure the consumption of the DUT alone. Draw the schematic and the symbol of the Mirror Full-Adder (Fig. 2a of Alioto and Palumbo paper). Leave the transistor sizes at their default values for now; you will do the transistor sizing later. As for the inverter, use vdd_inherit and gnd_inherit for the supplies. Draw the schematic of the testbench according to Figure 3. Use vpulse cells from library analoglib for the input stimulus sources (instances VA, VB, and VC). Voltage source V4 is used to measure the current drawn by the DUT. Make sure to name the net vdd_dut as shown in the figure. To connect the power supply of the DUT to the node vdd_dut, add a netset property to the DUT instance as follows: Open the Edit Object Properties dialog window of the DUT. Click on the Add button in the dialog window to add a property. Complete the pop-up dialog as shown in Figure 1. Figure 1: Dialogs for setting netset property 2/7

3 Figure 2: Inverter schematic DUT Figure 3: Testbench for Full Adder 3/7

4 4. TRANSISTOR SIZING Size the transistors of the FA to meet the following input-to-output propagation delay specifications: C in to C o (carry propagation): Any input (A, B, or C i ) to any output (S or C o ): < 0.5 ns < 1ns As the load on the outputs is small and the speed specifications are relaxed, a simple sizing strategy is to start with minimum size transistors, and then increase the sizes as necessary, starting from the outputs. (To minimize the area and power of the FA, the transistors should not be larger than needed to reach the specs.) When there are n stacked transistors in the pull-down or pull-up network, make these transistors n times wider. Make the PMOS 2.5x wider than the corresponding NMOS. Once you have done an initial sizing: Run a transient simulation to verify the functionality of the FA cell. Figure 4 shows example input waveforms for the functional verification. (Use 100 ps rise and fall time, and 0 V and 3.3 V for the logic levels.) Adjust the sizes of the inverters generating C o and S (inside the FA) so that they can drive the load (rise and fall times 200ps). If you find it necessary to increase the inverter size by a large factor (i.e. more than 3) you may also have to scale the transistors driving these inverters. To verify the fall and rise times of C o and S, and to measure the carry propagation delay, use the stimulus shown in Figure 5. A B C i 10 ns Figure 4: Stimulus for functional verification A B C i 1 ns Figure 5: Stimulus for carry propagation measurement 4/7

5 A sort of eye-diagram can be used to visualize the carry propagation delays of all four C o transitions. The following expression (in the calculator) will display the diagram for output C o (you can use the special functions menu to generate this): eyediagram( VT( /Co ) 1e-09 8e-09 2e-09 ) Overlaying the diagrams for C o and C i will give a plot similar to that shown in Figure 6. Save this eyediagram for the final report. Q2: What is the maximum carry propagation delay of your FA cell? Figure 6: Eye Diagram for Carry Propagation 5. DESIGN VERIFICATION To verify that the delay specifications are fulfilled for all transitions, you have to simulate all possible transitions that cause a change of the outputs. To do this, proceed as follows: Change the stimulus sources in the testbench (VA,VB,VC) to vpwlf sources (analoglib library). Set the PWL file name parameter of these sources to the names given in Table 1. Adjust the Delay time parameter of source VC such that all input signal transitions arrive at the same time at the DUT inputs. As the propagation delay of an inverter is shorter than the carry propagation delay of the FA, you will need to set it to a negative value. To find out the exact value to put, you can first run a simulation (see next point) and inspect the waveforms at nodes A, B, and C i. 5/7

6 Source Name VA VB VC Stimulus file path <your home directory>/fa_stim_a.scs <your home directory>/fa_stim_b.scs <your home directory>/fa_stim_c.scs Table 1: PWL file names Set up a transient simulation with a stop time of 102 ns. To measure the power consumption of the FA, save the current through voltage source V4. Run the simulation. Use the calculator to visualize results: Construct an eye diagram for all inputs and outputs as described in the previous section. Save the calculator expressions as output expressions so they will be automatically plotted after each simulation run (Figure 7). In the waveform window, use Curves Edit Assign to Y Axis to display all diagrams on the same y-axis. Figure 7: Saving output expression for eye diagram Adjust the transistor sizing if you find that the specifications are not met. When all the specifications are met, save a screenshot of the following two eye diagrams for your final report and complete the table of Q3. Figure 8 shows an example eye diagram. 1) Eye diagram with all inputs (A,B,C i ) and S 2) Eye diagram with all inputs and Co Q3: Report the average power consumption and the measured delays in the following table: Average Power (in µw) Propagation delay (in ps) Transition max min S falling S rising C o falling C o rising 6/7

7 Figure 8: Example eye diagram Do NOT forget to answer all questions save all screenshots for the final report return this document to the assistants in your room at the end of the session. 7/7