Introduction to Full-Custom Circuit Design with HSPICE and Laker

Transcription

1 Introduction to VLSI and SOC Design Introduction to Full-Custom Circuit Design with HSPICE and Laker Course Instructor: Prof. Lan-Da Van T.A.: Tsung-Che Lu Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2009

2 Environment Setup Tool Pietty Xming

3 Environment Setup (Xming) Open Xming No Access Control

4 Environment Setup (Pietty) Server: hwlab01.cs.nctu.edu.tw ~ hwlab08.cs.nctu.edu.tw Password could be changed on hwlab01 only. Your IP:0

5 Simulation with HSPICE Introduction to VLSI and SOC Design

6 Annotation (with * start) Part 1 Part 2 A Typical SPICE Script * cmos inverter.include mosistsmc180.sp Model File * sub circuit component netlist.subckt inv in out gnd vdd ma out in gnd gnd NMOS L=0.18u W=0.36u mb out in vdd vdd PMOS L=0.18u W=0.72u.ends Transistor Type * voltage source X1 in out gnd vdd inv v1 vdd 0 1.8V v2 gnd 0 0V v3 in 0 pulse ( ns 0.01ns 0.01ns 0.5ns 1ns) in VDD GND out Part 3 * simulation environment.option post.tran 0.05ns 3ns Specification Measurement.meas tran td1 trig v(in) val=0.9 rise=1 targ v(out) val=0.9 fall=1.meas tran td2 trig v(in) val=0.9 fall=1 targ v(out) val=0.9 rise=1.end End of the script

7 Basic Syntax in HSPICE (1/2) MOS Transistor: ma out in gnd gnd NMOS L=0.18u W=0.36u Mx (drain) (gate) (source) (body) (Type of MOST) + L=(length) W=(width) Capacitor: C p : There s a 5pF capacitor C1 between node 1 & node 0 Resistor: R k : There s a 5k(ohm) resistor R1 between node 2 & node 0 DC Voltage Source V1 VDD 0 1.8V : There s a 1.8V voltage source V1 between node VDD & node 0 Notice: Node 0 is considered as GROUND in SPICE simulation. Never use a node name with numbers in the front part. (Ex: 2P, 3A)

8 Basic Syntax in HSPICE (2/2) Subcircuit Syntax:.subckt inv in out gnd vdd ma out in gnd gnd NMOS L=0.18u W=0.36u mb out in vdd vdd PMOS L=0.18u W=0.72u.ends This is a sub-circuit called inv which has 4 nodes called in, out, gnd and vdd Subcircuit Calls: X1 in out gnd vdd inv A subcircuit X1 is called by netlist and its type is inv

9 Analysis Type Transient Analysis:.tran 0.05ns 3ns Above syntax will ask SPICE to simulate the circuit s waveform from 0ns to 3ns with a interval of 0.05ns. DC Analysis:.dc vds Above syntax will ask SPICE to simulate the circuit s DC operating point as the variable vds changing from 0 to 1.8 with a interval of 0.05.

10 Pulse Source Function Figure Source: 王朝琴, SPICE Training Manual, CIC, July, 2005

11 Piecewise Linear Function Figure Source: 王朝琴, SPICE Training Manual, CIC, July, 2005

12 MEASURE: Application Examples Figure Source: 王朝琴, SPICE Training Manual, CIC, July, 2005

13 Run HSPICE Job Concluded Command: hspice i xxx.sp -o xxx.lis If Job Aborted, see xxx.lis file for detailed imformation. The measured specifications and power consumption will be listed in.lis file. The simulated waveform will be saved in.tr0 file.

14 .meas Output Format in.lis file ****** transient analysis tnom= temp= ****** td1= E-12 targ= E-10 trig= E-10 td2= E-11 targ= E-10 trig= E-10 ***** job concluded

15 Waveform Viewer - nwave (1/3) File Open Command: nwave &.tr0 *.*

16 Waveform Viewer - nwave (2/3) Get Signals Choose input & output node

17 Waveform Viewer - nwave (3/3) Press 100% button

18 Layout with Laker Introduction to VLSI and SOC Design

19 CMOS Cross-section Figure Source: F. Maloberti, Analog Design for CMOS VLSI Systems N. H. E Weste and D. Harris, CMOS

20 NMOS Contact Poly Diffusion Width (W) Length (L) NIMP PIMP Metal1 Figure Source:

21 PMOS Contact Metal1 NIMP PIMP Diffusion NWell Poly Figure Source:

22 Laker - Create a New Library (1/1) Library New Create a new library

23 Laker - Create a New Library (2/2) Enter library name /cad/cbdlib/cic18/laker/laker.tf

24 Laker - Create a New Cell Cell New

25 Laker Change Grid Change Gird 0.01

26 Laker - Hotkeys r: rectangle u: undo k: ruler Shift + k: remove rulers Delete: delete shapes or lines Esc: back to cmd(selecting) Shift + p: polygon Ctrl + z: zoom in Shift + z: zoom out f: fit design c: copy m: move p: path l: text cmd(selecting) + ctrl + a: select all

27 Inverter (1/3) Schematic Stick Diagram VDD P-diff Vin N-diff Vout GND Figure Source:

28 Inverter (2/3) Figure Source:

29 Inverter (3/3) Figure Source:

30 0.18um 1P6M Process Layers Diffusion N-Well P Implant N Implant CONT Poly Metal 1 VIA

31 Verification and Extraction with Calibre DRC (Design Rule Check) Check for design rule violations LVS (Layout versus Schematic Check) Check for inconsistencies between the physical layout and the schematic PEX (Parasitic Extraction) / LPE (Layout Parameter Extraction) Extract layout parameters, such as transistors, parasitic capacitor, and parasitic resistors Extracted netlist

32 DRC with Calibre (1/3) Verify Calibre Run DRC /cad/cbdlib/cic18/calibre/calibre_drc/rule.drc

33 DRC with Calibre (2/3) Must be selected!

34 DRC with Calibre (3/3) Total Errors Count Clear Highlight The errors of DRC must be modified for error free! Double Click Detailed Information about errors Highlight on your layout

35 Lab Requirement Copy is strictly prohibited, and doing the assigned labs on your own is required. Otherwise, you will get zero score for no excuse. Please notice the lately delivered reports will not be accepted after due date. Detailed information and report format will be announced on the course forum/website. The designate model file (mosistsmc180.sp) can be downloaded from SPICE and Verilog code link in textbook s website. The course forum is available now. Any question/ discussion can be posted on board or TAs.