Lecture 7: SPICE Simulation
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1 Lecture 7: SPICE Simulation Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design
2 Outline Introduction to SPICE DC Analysis Transient Analysis Subcircuits Optimization Power Measurement Readings
3 Introduction to SPICE Simulation Program with Integrated Circuit Emphasis Developed in 1970 s at Berkeley Many commercial versions are available HSPICE is a robust industry standard Has many enhancements that we will use Written in FORTRAN for punch-card machines Circuits elements are called cards Complete description is called a SPICE deck 3
4 Writing Spice Decks Writing a SPICE deck is like writing a good program Plan: sketch schematic on paper or in editor Modify existing decks whenever possible Code: strive for clarity Start with name, , date, purpose Generously comment Test: Predict what results should be Compare with actual Garbage In, Garbage Out! 4
5 Example: RC Circuit * rc.sp * David_Harris@hmc.edu 2/2/03 * Find the response of RC circuit to rising input * Parameters and models.option post Vin R1 = 2K C1 = 100fF + Vout - * Simulation netlist Vin in gnd pwl 0ps 0 100ps 0 150ps 1.0 1ns 1.0 R1 in out 2k C1 out gnd 100f * Stimulus.tran 20ps 1ns.plot v(in) v(out).end 5
6 Result (Graphical) 6
7 Sources DC Source Vdd vdd gnd 2.5 Piecewise Linear Source Vin in gnd pwl 0ps 0 100ps 0 150ps 1.0 1ns 1.0 Pulsed Source Vck clk gnd PULSE ps 100ps 100ps 300ps 800ps PULSE v1 v2 td tr tf pw per v2 td tr pw tf v1 per 7
8 SPICE Elements Letter R C L K V I M D Q W X E G H F Element Resistor Capacitor Inductor Mutual Inductor Independent voltage source Independent current source MOSFET Diode Bipolar transistor Lossy transmission line Subcircuit Voltage-controlled voltage source Voltage-controlled current source Current-controlled voltage source Current-controlled current source 8
9 Units Letter Unit Magnitude a atto f fempto p pico n nano 10-9 u micro 10-6 m milli 10-3 k kilo 10 3 x mega 10 6 g giga 10 9 Ex: 100 femptofarad capacitor = 100fF, 100f, 100e-15 9
10 DC Analysis * mosiv.sp * Parameters and models.include '../models/ibm065/models.sp'.temp 70.option post * Simulation netlist *nmos Vgs g gnd 0 Vds d gnd 0 M1 d g gnd gnd NMOS W=100n L=50n V gs 4/2 I ds V ds * Stimulus.dc Vds SWEEP Vgs end 10
11 I-V Characteristics nmos I-V V gs dependence Saturation 11
12 MOSFET Elements M element for MOSFET Mname drain gate source body type + W=<width> L=<length> + AS=<area source> AD = <area drain> + PS=<perimeter source> PD=<perimeter drain> 12
13 Transient Analysis * inv.sp * Parameters and models.param SUPPLY=1.0.option scale=25n.include '../models/ibm065/models.sp'.temp 70.option post * Simulation netlist Vdd vdd gnd 'SUPPLY' Vin a gnd PULSE 0 'SUPPLY' 50ps 0ps 0ps 100ps 200ps M1 y a gnd gnd NMOS W=4 L=2 + AS=20 PS=18 AD=20 PD=18 M2 y a vdd vdd PMOS W=8 L=2 + AS=40 PS=26 AD=40 PD=26 * Stimulus.tran 0.1ps 80ps.end 13 a 8/2 4/2 y
14 Transient Results Unloaded inverter Overshoot Very fast edges 14
15 Subcircuits Declare common elements as subcircuits.subckt inv a y N=4 P=8 M1 y a gnd gnd NMOS W='N' L=2 + AS='N*5' PS='2*N+10' AD='N*5' PD='2*N+10' M2 y a vdd vdd PMOS W='P' L=2 + AS='P*5' PS='2*P+10' AD='P*5' PD='2*P+10'.ends Ex: Fanout-of-4 Inverter Delay Reuse inv Shaping Loading Shape input Device Under Test Load a b c d e X1 X2 X3 X Load on Load 512 X5 256 f 15
16 FO4 Inverter Delay * fo4.sp * Parameters and models param SUPPLY=1.0.param H=4.option scale=25n.include '../models/ibm065/models.sp'.temp 70.option post * Subcircuits global vdd gnd.include '../lib/inv.sp' * Simulation netlist Vdd vdd gnd 'SUPPLY' Vin a gnd PULSE 0 'SUPPLY' 0ps 20ps 20ps 120ps 280ps X1 a b inv * shape input waveform X2 b c inv M='H' * reshape input waveform 16
17 FO4 Inverter Delay Cont. X3 c d inv M='H**2' * device under test X4 d e inv M='H**3' * load x5 e f inv M='H**4' * load on load * Stimulus tran 0.1ps 280ps.measure tpdr * rising prop delay + TRIG v(c) VAL='SUPPLY/2' FALL=1 + TARG v(d) VAL='SUPPLY/2' RISE=1.measure tpdf * falling prop delay + TRIG v(c) VAL='SUPPLY/2' RISE=1 + TARG v(d) VAL='SUPPLY/2' FALL=1.measure tpd param='(tpdr+tpdf)/2' * average prop delay.measure trise * rise time + TRIG v(d) VAL='0.2*SUPPLY' RISE=1 + TARG v(d) VAL='0.8*SUPPLY' RISE=1.measure tfall * fall time + TRIG v(d) VAL='0.8*SUPPLY' FALL=1 + TARG v(d) VAL='0.2*SUPPLY' FALL=1.end 17
18 FO4 Results 18
19 Optimization HSPICE can automatically adjust parameters Seek value that optimizes some measurement Example: Best P/N ratio We ve assumed 2:1 gives equal rise/fall delays But we see rise is actually slower than fall What P/N ratio gives equal delays? Strategies (1) run a bunch of sims with different P size (2) let HSPICE optimizer do it for us 19
20 P/N Optimization * fo4opt.sp * Parameters and models param SUPPLY=1.0.option scale=25n.include '../models/ibm065/models.sp'.temp 70.option post * Subcircuits global vdd gnd.include '../lib/inv.sp' * Simulation netlist Vdd vdd gnd 'SUPPLY' Vin a gnd PULSE 0 'SUPPLY' 0ps 20ps 20ps 120ps 280ps X1 a b inv P='P1' * shape input waveform X2 b c inv P='P1' M=4 * reshape input X3 c d inv P='P1' M=16 * device under test 20
21 P/N Optimization X4 d e inv P='P1' M=64 * load X5 e f inv P='P1' M=256 * load on load * Optimization setup param P1=optrange(8,4,16) * search from 4 to 16, guess 8.model optmod opt itropt=30 * maximum of 30 iterations.measure bestratio param='p1/4' * compute best P/N ratio * Stimulus tran 0.1ps 280ps SWEEP OPTIMIZE=optrange RESULTS=diff MODEL=optmod.measure tpdr * rising propagation delay + TRIG v(c)val='supply/2' FALL=1 + TARG v(d) VAL='SUPPLY/2' RISE=1.measure tpdf * falling propagation delay + TRIG v(c) VAL='SUPPLY/2' RISE=1 + TARG v(d) VAL='SUPPLY/2' FALL=1.measure tpd param='(tpdr+tpdf)/2' goal=0 * average prop delay.measure diff param='tpdr-tpdf' goal = 0 * diff between delays.end 21
22 P/N Results P/N ratio for equal delay is 2.9:1 t pd = t pdr = t pdf = 17.9 ps (slower than 2:1 ratio) Big pmos transistors waste power too Seldom design for exactly equal delays What ratio gives lowest average delay?.tran 1ps 1000ps SWEEP OPTIMIZE=optrange RESULTS=tpd MODEL=optmod P/N ratio of 1.8:1 t pdr = 18.8 ps, t pdf = 15.2 ps, t pd = 17.0 ps P/N ratios of 1.5:1 2.2:1 gives t pd < 17.2 ps 22
23 Power Measurement HSPICE can measure power Instantaneous P(t) Or average P over some interval.print P(vdd).measure pwr AVG P(vdd) FROM=0ns TO=10ns Power in single gate Connect to separate V DD supply Be careful about input power 23
24 Summary Various analysis with SPIC Optimization and measurement Useful tool for transistor-level delay, power, process variation evaluations Can be the gold model for gate-level and higher Can be useful for novel device and circuit studies Next lecture Combinational circuit design Reading
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