Yuan-Piao Lee Te-Hsiu Chen Chienkuo Technology University, ChungHua, Taiwan, ROC

Transcription

1 Select the MODEL set HSPICE simulation results Yuan-Piao Lee Te-Hsiu Chen Chienkuo Technology University, ChungHua, Taiwan, ROC ABSTRACT To the the HSPICE design of circuit is quite convenient, this paper investigates the application of HSPICE in amplifier design MODEL set output. MODEL for several different settings, comparing different front-end analog simulation and posterior segment, judge the correctness and conclusions are the HSPICE correct settings on the MODEL. In this study, analysis and comparison, conclusion the best setting to take in a good database program default. MODEL set into default, the simulation software will be based on the width and length of the transistor circuit design, automatically find the most suitable corresponding to the size of the element MODEL. However, if set to the MODEL = level 49, the simulation software will be elected element MODEL size does not fit. In our study concludes, will make MODEL choose to reach the best situation, with the creative design correct circuit design, the surplus will be able to design the perfect chip. Key words: HSPICE, MODEL, Level 49, OPAMP, simulation software I. INTRODUCTION In recent years, the technology of the process has entered the deep submicron (Deep Sub-micron) [1], but the motif at the transistor level circuit simulation, SPICE software is still the most representative in the integrated circuit design. Design environment, commercial SPICE simulation software to HSPICE, PSPICE [2], SBTSPICE and IsSPICE [3]. HSPICE built-component model is complete, all kinds of circuit simulation and analysis of full-featured, and therefore, many integrated circuit products, the use of the design and simulation of the HSPICE auxiliary line, and the excellent results presented. The early industry HSPICE MODEL with the standard model of program content, provides readers modeling concepts to understand the parameters of the model in the design and layout process, and how they affect the performance of the circuit. Modeling program, test wafer (test chip) plays an important role. Test chip, many test key (test key) [4] or test structure (test structure). The test key main purpose of the monitoring process data is used to retrieve the device parameters. HSPICE 10

2 Circuit Main Body ISSN International Journal of Technology People Developing, Volume 3, Number 1, April 2013 program, the MODEL statement commonly used in semiconductor components or user self-built components of the linear equivalent model [5-10]. Model parameters and the default size chosen by the the device processing plant, there are many different levels of complexity version HSPICE "LEVEL N" and termed, N digital 1,2,3..., the larger the number, calculation parameters for complex. Improve integrated circuit process, the actual occurrence of the element for the accuracy of the model used in the design process, the impact on circuit simulation results. Model selection and design of the nature of the product is associated with, the designer must be familiar with the product and the circuit, what parameters are the most sensitive and the most critical parameters. * Title Description Define database Definition Power Crystal and circuit design Analysis of patterns Data output components, Section IV experience: for explore the simulation results of the circuit, and to compare, section V of questions and discussion, as well as the final conclusions. II. THE HSPICE PROGRAM AND ARCHITECTURE HSPICE is circuit simulation software, designed to simulate the behavior of the circuit and features. It is based on the various components of transistors, diodes, resistors and capacitors, model-based, numerical methods to calculate circuit node voltage and current changes. The nonlinear circuit system can calculate their approximate solution, from the results of the correctness of often and component model, the algorithm has a close relationship. The HSPICE mainly offers steady state, transient and small-signal frequency response simulation. This article is based on the HSPICE design of the operational amplifier (OPAMP: Operational Amplifier) as the example of the study..end (End of statement) Fig. 1. HSPICE procedure structure M5 M6 M7 M15 M12 This article a total of six, Section I M8 M9 M1 M2 M14 out is the Introduction, Section 2 HSPICE architecture: explaining and illustrating the design of the circuit, Section III MODEL: use the syntax description for the model parameters use and VCM VCM VIN M10 M11 M3 M4 R1 C1 M16 Fig. 2. OPAMP circuit diagram M17 M13 11

3 Figure 2 of this paper the design and planning of the operational amplifier, the design is based on metal oxide semiconductor silicon field-effect transistor (MOSFET, Metal Oxide Semiconductor Field-Effect Transistor) consisting referred to as the "M" in the following figure. Upper left dashed block in the figure for the current mirror, including M5, M6, M8, M9, M10, M11, M7, M15, M12, and R1. The intermediate dashed box for the differential amplifier contains M1 is, M2, and as impedance M3 and M4. The center-right of the dashed block this paper, the design of the feedback circuit M14 and C1, and the M15, M17, M16, supply feedback circuit required current. The design for the twelve (Two stage) op amp architecture contains preamp, post-feedback. Front for the M1, M2 differential on the Vin + and Vin-voltage signal into a current signal, plus M3, M4 resistor current signals transition to a voltage signal. After feedback part forward zoom common source very connected to the M13 and M12 supply current feedback amplifier is a common source of M14 and feedback capacitor C1 is connected and use the M15, M16, and M17 provide the required current. Feedback circuit for frequency compensation system, moving the zero increase phase margin (Phase Margin), to improve system stability. III. MODEL GAP AND SELECT Model parameters used in SPICE program (Model parameter), most of the direct component manufacturers such as TSMC, UMC and other parameters (such as diodes, BJT, FET, etc.). Generally in the circuit design on a number of common components, such as resistors, capacitors, inductors, diodes, transistors... and so on. These components of the model parameters, component manufacturers have been adjusted to the error of less than two percent and the actual curve. Therefore, depending on the model parameters are sufficient to reflect the real situation. In addition to the other set or change little special components, general IC designers are not components of the MODEL parameter. Table 1 example of some of the more commonly used components MODEL set syntax. Table 1. The syntax of the devices Devices Syntax Resistance R name, Positive node, Negative node, Model name, R resistance value, TC1 first-order temperature coefficient, TC2 second-order temperature coefficient Capacity C name, Positive node, Negative node, Model name, C resistance value, TC1 first-order temperature coefficient, TC2 second-order temperature coefficient MOSFET M name, Drain node, 12

4 Gate node, Source node, Substrate node, Model name, L length W width Bipolar Q transistors Name, Collector node, Base node, Emitter node, Model name, AREA emitter area product factor Table 2 MOSFET process and device model level recommended table Channel length of SPICE model MOSFET devices applicable More than 5μm LEVEL 2 More than 3μm LEVEL 3 More than 1μm LEVEL 6, 13 (BSIM1), LEVEL 28 Sub-half micron LEVEL 28, process & more LEVEL 49 (BSIM3V3) Deep-submicron LEVEL 9, process & more LEVEL 49 (BSIM3V3) Advances in integrated circuit process, in addition to manufacturing equipment updates, so that element into the deep sub-meter or nanometer era. The accuracy of the components in the circuit simulation is more stringent requirements, and thus developed a variety of different levels (Level) component model parameters. Table 2 shows the MOSFET process, the appropriate SPICE model parameters. Since SPICE MODEL LEVEL 49 (BSIM3V3) is recognized as the most suitable for the modern component level parameters. Next, the study will explore to LEVEL 49 SPICE program set. Table 3 for this design OPAMP part of simulation program, using the National Chip Implementation Center (CIC, National Chip Implementation Center) provided 0.35μm 2P4M (2-Polysilicon-Metal) CMOS standard process, and is divided into (a.) program MODEL setting, and (b.) program in two ways MODEL set. First define Library, circuit power supply, the same way as part of the status of both designs. Followed by the circuit design, the design of this part of the status of both methods is no different. Followed by the circuit design, the design of this part of the status of both methods is no different. Finally, set the analysis parameters MODEL analytical methods AC analysis, as well as the output mode voltage gain and phase margin analysis. Short, only used in Table 1 (b.) simulation program to MODEL set, and set.model nch nmos level=49 and.model pch pmos level=49. It means that the N-channel MOSFET Model is Level 49, and the P-channel MOSFET Model is Level

5 Table 3. Partial simulation program (a.) program without.model setting.lib 'mm0355v.l' TT.GLOBAL VDD GND VDD VDD GND DC 5v M vdd pch L=0.35u W=60u M vdd pch L=0.35u W=60u (a.) program with.model setting.lib 'mm0355v.l' TT.GLOBAL VDD GND VDD VDD GND DC 5v M vdd pch L=0.35u W=60u M vdd pch L=0.35u W=60u V1 2 GND DC 2.5V V2 3 GND DC 2.5V AC 1V.OP.AC DEC Hz 10GHz.PRINT AC VDB(out) VP(out).option post.end V1 2 GND DC 2.5V V2 3 GND DC 2.5V AC 1V.model nch nmos level=49.model pch pmos level=49.op.ac DEC Hz 10GHz.PRINT AC VDB(out) VP(out).option post.end IV. EXPERIENCE Fig. 3. HSPICE Pre-simulation results comparison, the above waveform voltage gain and lower Pictured phase. Solid line in the vertical diagram.model setting, the dotted line is a. MODEL set of simulation results. Table 3 OPAMP the HSPICE program is (a.) program MODEL setting, and (b.) program MODEL set two conditions simulation results shown in Figure 3 and Figure 4 below. The simulation results of comparison, and FIG 4 is a Post-sim (Post-simulation) simulation results. In Figure 3 is a pre-sim simulation result, a waveform diagram of the voltage gain of the circuit of OPAMP (Voltage Gain), the following diagram of the waveform of the phase (PHASE).In the figure, the solid line is in the simulation program not specifically ".Model" setting, the dashed line is the result of having ".Model" of the settings. As can be seen in the Figure, HSPICE program is without.model setting, then the voltage gain is about 49.9dB, and the unity-gain frequency is about 1.12GHz with phase of degrees, and phase margin of 98.1degrees. HSPICE program if ". MODEL setting, the voltage gain of about 41.0 db and a unity gain 14

6 frequency MHz, and the phase is degrees phase margin equal to = degrees. Here to remove all values system of computer graphics in the amount of measured income. Fig. 4. HSPICE Post-simulation results comparison, the above waveform voltage gain and lower Pictured phase. Solid line in the vertical diagram.model setting, the dotted line is a.model set of simulation results In Figure 4 for Post-sim simulation results on the diagram of the waveform the OPAMP circuit voltage gain (Voltage Gain) following figure waveform phase (Phase). The solid line in HSPICE simulation program.model settings, dashed line has. MODEL set of results. As can be seen in Figure HSPICE program absence.model set the voltage gain of about 51.6dB, its unity-gain frequency (Unit Gain Frequency) of 1.01GHz, and phase degrees, the phase margin is equal to = degrees. The HSPICE program settings.model, voltage gain of approximately 40.2 db, unity gain frequency of MHz, and the phase of degrees phase margin equal to = 82.6 degrees. Here also remove all values system of in computer graphics in the measurement obtained. Figure 5 is comparison of the simulation results of the Pre-sim and Post-sim in HSPICE MODEL. The voltage gain of the figure, the figure below shows the phase. The solid line is the Pre-sim, dashed line, compared with the simulation results of the Post-sim. Figure 6 is the OPAMP of analog circuit layout size to 121μm x 116μm. Figure in the upper left block for the current mirror, the middle of a block preamp, lower right block for post-amplification. The layout of the design of such circuits need to pay attention to many skills, mainly in order to reduce the interference on the analog system does not match and noise effects. The transistor layout should strive symmetry to avoid any mismatch, otherwise it will lead to a greater offset voltage. At the same time, the the layout line width (Line Width) narrow, parallel points of contact (Contact) insufficient and parallel channel (Via), the impact of the current liquidity and caused by the parasitic resistance of the line is too large. Furthermore, the metal wire (Metal Line) and polysilicon lines (Ploysilicon Line) in the overlap between the different layers (Level) (Overlap), and the same distance between the layers (Space), and length, affect the value of the parasitic 15

7 capacitance. Fig. 5. Pre-sim and Post-sim had no MODEL simulation results comparison. The picture above shows the voltage gain Pictured phase (Phase). Both figures solid line Pre-sim, the dotted line is the results of the Post-sim Fig. 6. The OPAMP circuit layout, the upper left block for the current mirror, the middle of a block preamp, lower right block for post-amplification In Figure 5, the gap between the Pre-SIM and Post-sim, mainly is because the Post-sim plus circuit layout parasitic resistance and capacitance caused by the difference. In Figure 5, the gap between the pre-sim and Post-sim, mainly because of the Post-sim consider parasitic resistance and capacitance on the circuit layout. Although there is a slight error of the simulation results of both, as shown in Figure 5, the large part of the curve is almost overlap, within the actual occurrence of still-permissible range. V. QUESTIONS AND DISCUSSINGS Discussed in the previous section, in the HSPICE program should use the 49-level Model set, but the LEVEL set to between 49 and blank set, has a significant gap. At the same time, significant gaps circuit terror Bureau no correlation. At this point, check HSPICE program and explore. Usually HSPICE circuit simulation output file shown in Figure 7, the important information in the large part of the simulation process will be here show that this output is the pre-sim the results. Figure 8 shows HSPICE circuit simulation output file for the Post-sim, Post-sim simulation program from the layout parameter extraction software (Calibre-PEX), the software outputs reaction Bureau of real terror situation. Sixth teeth MOSFET (m6) pole (Three Finger Gates) constitute the actual occurrence of the trigeminal gate layout is divided into m6, 2, and 3 trigeminal. Therefore, the truth m6 Drain total current m6, 2, and three 3. Because of the layout parameter extraction software (Calibre-PEX) simulation, changing the transistor number Therefore, it still need to be 16

8 careful and adjust subsequent comparative. In such a case, the Figure 7 pieces of the seventh transistor (m7) that is, the layout parameter extraction software changed to Figure 8, the sixth teeth transistor (m6). Fig. 7. HSPICE Pre-sim circuit simulation exports the shelf (some),there is no appointed MODEL Fig. 8 HSPICE Post-sim circuit simulation exports the shelf (some),there is no appointed MODEL Fig. 9 HSPICE Post-sim circuit simulation exports the shelf (some),without appointed MODEL, the single electric crystal was drawn very much the electric current has already been combined By comparing Figure 7, Figure 9, Figure 10 (a), and Figure 10 (b), the output file biggest difference as a model column is different. Have set ".MODEL = level 49" condition, the model bar displays are 0: PCH or 0: NCH. Under the condition of no set ".MODEL", the model column shows the "nch.1 nch.12" "pch.1 to pch.12. View of the investigation, the HSPICE 0.35μm process provided by the National Chip Implementation Center (CIC) MODEL file "mm0355v" nch.1 to nch.12 with pch.1 to pch.12 are representatives of the different sizes of the transistors. The HSPICE program blank (on behalf of the default), the simulation software will be based on the design of the transistor width (W) and length (L) of different automatic seeking to meet the most suitable for the size of the MODEL (nch.1 to nch.12 and pch.1 to pch.12 in Model). However, if the HSPICE program 17

9 set MODEL = level 49, the simulation software will optionally with type Level is equal to 49 of the transistor parameters. Of course, the worst condition set by the Model Model programs set but not given a Level value. This case, the simulation software put Level automatically set to 1, this time, the vast majority of parameters tragically brief, the most accurate of the three methods. (a) (b) Fig. 10. HSPICE (a) Pre-sim (b) Post-sim the circuit simulation output file (part), specify the MODEL = level 49 VI. CONCLUSION In this study, analysis and comparison, conclusion the best the HSPICE of the MODEL is set to take in a good database program default, which is blank. Process MODEL file provided by the National Chip Implementation Center "mm0355v" contains different sizes of transistors. MODEL set into default, the simulation software will be based on the width and length of the transistor circuit design, automatically find the most suitable corresponding to the size of the element MODEL. The rest of the method of setting, such as the.model = Level 49 conditions, the software simulation process optionally together with the component types Level is equal to 49 of transistor parameters, but the size of the element MODEL is not necessarily the most suitable. The worst situation is the program settings. Model but not given a Level value, in this case, the simulation software put Level is automatically set to 1, this time, the vast majority of the parameters tragically brief, three methods most inaccurate way. I conclude that make MODEL choose to reach the best situation, high efficiency using HSPICE simulation software. With perfect design creativity, the correct type of circuit design, good temperature compensation, power range planning properly, and the circuit effective performance tuning, will be able to design a trade surplus perfect 18

10 chip. ACKNOWLEDGEMENTS The depth to thank the National Chip Implementation Center (CIC, National Chip Implementation Center) to provide free research simulation software and component parameters required resources. And the founding of the University of Science and Technology, Department of Electrical Engineering integrated circuit simulation and design laboratory, provision of computer equipment and technical guidance. REFERENCE [1] G. Tulunay and S. Balkir, "Synthesis of RF CMOS Low Noise Amplifiers," in Circuits and Systems, ISCAS IEEE International Symposium on, 2008, pp [2] M. T. Bina and A. K. S. Bhat, "Averaging Technique for the Modeling of STATCOM and Active Filters," Power Electronics, IEEE Transactions on, vol. 23, pp , [3] S. H. Lloyd, G. A. Smith, and D. G. Infield, "Design and construction of a modular electronic photovoltaic simulator," in Power Electronics and Variable Speed Drives, Eighth International Conference on (IEE Conf. Publ. No. 475), 2000, pp [4] A. Rode, A. McCamant, G. McCormack, and B. Vetanen, "A high-yield GaAs MSI digital IC process," in Electron Devices Meeting, 1982 International, 1982, pp [5] G. Tulunay and S. Balkir, "A Synthesis Tool for CMOS RF Low-Noise Amplifiers," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, pp , [6] Shu Wei and J. S. Chang, "THD of Closed-Loop Analog PWM Class-D Amplifiers," Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 55, pp , [7] P. K. Chan and J. Cui, "Design of Chopper-Stabilized Amplifiers With Reduced Offset for Sensor Applications," Sensors Journal, IEEE, vol. 8, pp , [8] S. Tuuna, Zheng Li-Rong, J. Isoaho, and H. Tenhunen, "Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 16, pp , [9] J. Lin, E. H. Toh, C. Shen, D. Sylvester, C. H. Heng, G. Samudra, and Y. C. Yeo, "Compact HSPICE model for IMOS device," Electronics Letters, vol. 44, pp , [10] X. Pan, W. B. Jone, and S. R. Das, "Performance Analysis for Clock 19

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