An 11-bit Two-Stage Hybrid-DAC for TFT LCD Column Drivers

Transcription

1 013 4th International Conference on Intelligent Systems, Modelling and Simulation An 11-bit Two-Stage Hybrid-DAC for TFT CD Column Drivers Ping-Yeh Yin Department of Electrical Engineering National Chi Nan University Puli, Nan-Tou 54561, Taiwan. Chih-Wen u Engineering and System Science National Tsing Hua University Hsinchu, Taiwan 30013, R.O.C. cwlu@mx.nthu.edu.tw Chih-Yu Hsu, and Yo-Sheng in Department of Electrical Engineering National Chi Nan University Puli, Nan-Tou 54561, Taiwan. Abstract This paper proposes an 11-bit two-stage hybrid- DAC for high-color-depth CD column drivers. To save the die area, the proposed DAC is composed of a 7-bit RDAC and a 4-bit cyclic-dac to render an 11-bit resolution. The worst DN/IN from post-layout simulation is 0.8/0.34 SB with 1 SB =. m. A three-stage class-b operational amplifier is connected as a unity-gain buffer to drive highly capacitive column lines of CD panel. The buffer s settling time to settle within 0.% of the final voltage is less than 4 μs. This hybrid- DAC prototype is implemented using 0.35-μm CMOS technology with a chip size of 1.36 mm. Keywords-CD, column driver, DAC, cyclic-dac, operatioal amplifier I. INTRODUCTION Modern improvements in liquid crystal display (CD) panels for multimedia products allow higher definition and greater color-depth [1] [3]. CD panels on these products have become larger with higher definition, and their image quality demands more precision. For CD-T applications with 10 3 (1,073,741,84) colors, its drivers must convert 10-bit digital input codes to analog levels, at which point the output buffers drive the data lines [4] [6]. An CD driver generally comprises column drivers, gate drivers, a timing controller, and a reference voltage source. Within the column driver, it contains shift registers, input registers, data latches, level shifters, DACs and output buffers, as shown in Figure 1 [7]. Among these components, DACs and output buffers determine the speed, resolution, voltage swing, and power dissipation of a column driver. Performing a higher color depth for CD drivers requires a higher DAC resolution and a larger circuit die area. Because of stringent display uniformity requirements, a resistor-string DAC (RDAC) is superiorly used in CD column drivers. However, the area of the RDAC and related routing lines are prohibitively large for a high-resolution data converter, making it impractical for using conventional column driver ICs in high color depth displays [8]. Recently, several linear DACs were used in the CD column driver ICs. The compensation of the nonlinear C characteristic is digitally made in the timing controller. Because the DAC is linear, additional two bits are required to compensate for the nonlinear C characteristic. The previous linear DACs include a cyclic-dac (CDAC) [4], [9], an embedded DAC [10], DACs with current modulation and interpolation [11], and a resistor-resistor-string DAC (RRDAC) without intermediate unity-gain buffers [8], [1]. Figure 1. CD column driver architecture. However, the high resolution CDAC architecture suffers from a long D/A conversion time. The embedded DAC architecture requires several input transistors with long widths and lengths for accurate matching, subsequently resulting in large area overhead for high-bit interpolation. Even though RRDAC is an area-effective architecture, this cascaded resistor string configuration is limited by the loading of the coarse interpolation resistor string from the fine interpolation resistor strings, subsequently affecting the reference voltages of the coarse interpolation resistor string [8]. The problem with loading by the fine voltage dividers can be avoided by using two intermediate unity-gain buffers in each channel driver, but doing so often causes offset errors to CD driver outputs, leading to display non-uniformity. Moreover, each output channel requires two additional buffers with increased power consumption. In 011, RRDAC with current compensation scheme has been proposed, which can avoid the aforementioned issues [1]. However, due to hundreds of output channels in a single column driver IC, the process variations of channel s current source transistors which are distant from the reference compensation current generator makes their compensation current offset with its ideal value. To alleviate the above problems, this work presents a two-stage hybrid-dac which is capable of simultaneously achieving high linearity and 11-bit resolution at a compact die size. Furthermore, a class-b buffer amplifier is used for output stage of each driver channel. The rest of this paper is organized as follows. Section II introduces proposed twostage hybrid-dac, and class-b buffer amplifier is also described. Section III summaries simulation results and Section I concludes the work /13 $ IEEE DOI /ISMS

2 b 10 b 9 b 8 b 7 b 6 b 5 b 4 REFH b 4 b 5 b 6 b 7 b 8 b 9 b 10 REFH 17 H H H REF Figure. Proposed 11-bit two-stage hybrid-dac. II. PROPOSED TWO-STAGE HYBRID-DAC A. Architectue of the Two-Stage DAC Achieving higher DAC resolution, two-stage architecture is excellent for area-efficiency. Figure shows the proposed 11-bit two-stage hybrid-dac in which a 7-bit RDAC and a 4-bit cyclic-dac are cascaded to reach 11-bit resolution. In a column driver chip, a 7-bit global resistor string ( ) is used. Each output channel has a 7-bit two-voltage selector, 4-bit cyclic-dac, and output buffer. Based on higher 7-bit data signals, the 7-bit voltage selector chooses two adjacent node voltages ( H and ) from the global resistor string and, then, connects them to the 4-bit cyclic-dac. The 4-bit cyclic-dac produces a voltage from one of the 16 levels between H and according to the lower 4-bit data signals and propagates it to the output buffer. B. A 7-bit RDAC with Two-oltage-Selection Scheme for First-Stage DAC Figure 3 shows a 7-bit RDAC with two-voltage-selection scheme as a first-stage DAC. The reference voltages are generated by the global resistor string and been connected to all channels 7-bit two-voltage selectors. Such a selector consisting of two sets of 7-bit one-voltage selector, mutually with a one-bit offset. One set outputs H, whereas the other outputs. The most-significant-bit (MSB) voltage is the difference between H and : H REFH REF = = 35m. (1) These 7-bit one-voltage-selectors are implemented by tree-type decoders. PMOS pass transistors are used for the upper part switches to pass high level voltages, while use NMOS pass transistors as the lower part switches to pass low level voltages. The 7-bit two-voltage-selector RDAC chooses a set of two adjacent voltages from the global resistor string and connects them to the subsequent 4-bit cyclic-dac for further voltage interpolation. 7-bit one-voltage selector 3 REF bit one-voltage selector Figure 3. A 7-bit RDAC with two-voltage-selection scheme. C. A 4-bit Cyclic-DAC for Second-Stage DAC Cyclic-DAC (CDAC) is a favorable architecture for compact CD driver design. The serial conversion CDAC has a facile structure with two identical capacitors and several switches, as shown in Figure 4. The charge redistribution is carried out through the switched-capacitors to produce an output voltage which value is based on ref according to the switches control signals. Although the active conversion is preferable for high resolution CDAC because of parasitic insensitivity operation, it consumes more power to finish more conversion cycles in a given time when number-of-bit increased. Figure 4. Serial conversion CDAC with two identical capacitors and several switches. To save CD column driver s power consumption and die area, a two-reference-voltage 4-bit CDAC is used for fine interpolation following the 7bit-RDAC, which is shown in figure 5. A little difference from the conventional one, two reference voltages H and are sampled by the CDAC with four switches and two identical capacitors. The lower 4-bit parallel input data signals are converted to a serial signal through a parallel-in to serial-out converter as shown in figure 6. The set signal is always 0 to pre-charge C1 and C to let the output voltage is initially, and the control signals sf 1 ~sf 5 are produced from shift registers in digital part. The CDAC requires one clock cycle to pre-charge C1 and C first, and then needs other four clock cycles to finish leastsignificant-bit (SB) voltage interpolation and propagates a voltage which value is between H and of 16 levels to the H 63

3 H Sw Sw1 Sw3 C Sw4 S SO set b 0 b 1 b b 3 C1 out Sw1 Figure 5. Proposed 4-bit cyclic-dac Sw Sw3 Sw4 Figure 6. Parallel-in to serial-out converter. output buffer. After each clock cycle during charge redistribution, the CDAC output voltage is the average value of C1 and C : + C1 C out =, () where C1 and C are the voltage sampled by the C1 and C after every clock cycle respectively. Including pre-charge cycle, it needs to spend five clock cycles to finish a 4-bit interpolation, and its final output voltage is: out + ref1 + ref + ref 3 + ref 4 =, (3) where ref 1, ref, ref 3 and ref 4 can be either or H according to the switches control signals. Figure 7 shows the control signals of CDAC switches when the input data signal b 3 b b 1 b 0 is The serial data signal S SO is from a parallel-in to serial-out converter, the Sw4 is just an inverted signal to the clock clk of this cyclic-dac, the Sw1 is the inverted signal of S SO AND with clk, the Sw is the result of S SO AND with clk, and the Sw3 signal is equal to the shift register signal s f1 AND with clk. Through this operation, the final output voltage is: out H + H =. (4) b 3 b b 1 b 0 = 1100 S SO = serial data signal Sw1 = S SO AND clk Sw4 = clk Sw3 = sf 1 AND clk Sw = S SO AND clk Figure 7. Control signals of CDAC switches when b 3b b 1b 0 is 1100 Other interpolation voltages of 16 levels between H and can be obtained similarly according to the 4-bit data signal. For WQUXGA (400 RGB 3840) displays with 60 Hz frame rate, the horizontal scanning time should not exceed 6.9 μs. In such a large format panel, the speed of 4-bit CDAC clock is only 0.75 MHz, which is not too fast owing to low-number-of-bit interpolation. D. A Class-B Output Buffer To drive the large format panel column line, a class-b operational amplifier is used as shown in Figure 8. M1~M4 is a bias circuit. M5 and M10 are respectively the current sources of PMOS input differential pair (M6 and M7) for the negative polarity inputs and NMOS input differential pair (M8 and M9) for the positive polarity inputs. The devices M11-M are constituted as folded active loads for the two differential pairs. M19-M0 and M1-M are two comparators to compare the voltages of in+ and in-. Once in+ is higher than in-, the output PMOS transistor M3 will turn on by the comparator M1-M s output, then the output voltage rises. Whereas in+ is lower than in-, the output NMOS transistor M4 will turn on by the comparator M19-M0 let the output voltage falls. When in+ and in- are equal, M3-M4 are cutoff, that is, the output voltage remains the same. To keep M3-M4 cutoff in the steady state to save power, the transistors size should be designed as follow: W W = 11 1, (5) 633

4 W W = 13 W W = 15 W W = W W W W and < > 16, (6), (7), (8) W W W W and > < 1 1, (9), (10) which is very large to sense a little voltage change between its input and output. III. SIMUATION RESUTS The following table summarizes the simulation result of the buffer amplifier. The quiescent current is only 5.9 μa and the settling time is under 4μs which is suitable for driving large format panels. TABE I. vdd Quiescent current Quiescent power Settling time (rising) Settling time (falling) PERFORMANCE OF BUFFER AMPIFIER μa 9.5 μw 3.7 μs (oad: R = 5 KΩ, C = 150 pf) 3.6 μs (oad: R = 5 KΩ, C = 150 pf) Figure 8. A 3-stage operation amplifier as a rail-to-rail output buffer. When in+ is equal to in-, equation (9) makes M0 in the triode region, and the gate voltage of M4 is approach to 0 to turn off M4. Similarly, equation (10) keeps M1 in the triode region, and the gate voltage of M3 is approach to vdd to turn off M3. Thus in the steady state, the output stage consumes no power. The output node of the class-b operational amplifier is connected to the port in- to form a unity-gain buffer. When the in+ higher than the output, the currents of M7 and M8 increase, and the currents of M6 and M9 decrease, then the gate voltages of M1 and M fall down. It causes the drain voltages of M1 and M rising. The drain voltage of M0 is still near 0, while the drain voltage of M1 falls down, turn on the output transistor M3, which charges the output node until the output voltage equals in+. Similarly, when in+ lower than the output, M3 is cutoff, while M4 turn on to discharge the output node. The output stage transistors size of M3 and M4 can be small but have sufficient driving capacity, because the sg ( gs ) of them may reach vdd during the transient state. The open-loop-gain of this three-stage buffer is: ro ro Aopen ( gm6ro ) gm0 4 gm ro ro + ( gm8ro) gm1 gm3. (11) = gm6gm0gm4ro + gm8gm1gm3ro 4 4 Appling a linear 11-bit grayscale data to the two-stage hybrid-dac, Figure 9 and Figure 10 show the post-layout simulation results of DN and IN respectively. The worst DN is 0.8 SB and the worst IN is 0.34 SB (1 SB = 0. m). Figure 11 shows the simulated output waveform with a 5 KΩ-resistance and 150 pf-capacitance load, as the digital data change from " " to " ". Settling time within 0.% of the final voltage is less than 4 μs. The proposed two-stage hybrid-dac was fabricated using 0.35-m CMOS technology. Figure 1 shows a die micrograph of this prototype with chip area of 1.36 mm. I. CONCUSIONS This paper presents an 11-bit two-stage hybrid-dac which is consisted of a 7-bit RDAC and a 4-bit cyclic-dac that can save die area. The proposed 11-bit hybrid DAC provide good linearity with DN/IN smaller than 0.5 SB (1 SB =. m). A class-b output buffer is also devised to drive the CD column line. The static current of this buffer is only 5.9 μa, and the settling time to drive a 150 pf capacitance load is below 4 μs. The chip was implemented by the 0.35-m CMOS technology with the die area of 1.36 mm. With these results, the proposed 11-bit hybrid-dac is highly promising for large-size high color-depth CD applications. Figure 9. The post-layout simulation DN of 11-bit hybrid-dac. 634

5 The authors would like to thank the National Chip Implementation Center (CIC), Taiwan, for the chip implementation. Figure 10. The post-layout simulation IN of 11-bit hybrid-dac. Figure 11. Output waveform with a 5 KΩ-resistance and 150 pfcapacitance load when the digital data change from to Figure 1. The Die micrograph of the proposed 11-bit hybrid-dac. ACKNOWEDGMENT REFERENCES [1] I. Pappas, S. Siskos, and C. A. Dimitriadis, A fast and compact analog buffer design for active matrix liquid crystal displays using polysilicon thin-film transistors, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 6, pp , Jun [] F. Su and W.-H. Ki, Component-efficient multiphase switchedcapacitor dc dc converter with configurable conversion ratios for CD driver applications, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 8, pp , Aug [3] C.-W. u, C.-C. Shen, and W.-C. Chen, An area-efficient fully R- DAC-based TFT-CD column driver, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 10, pp , Aug [4] M. J. Bell, An CD column driver using a switch capacitor DAC, IEEE J. Solid-State Circuits, vol. 40, no. 1, pp , Dec [5] J.-S. Kang, J.-H. Kim, S.-Y. Kim, J.-Y. Song, O.-K. Kwon, Y.-J. ee, B.-H. Kim, C.-W. Park, K.-S. Kwon, W.-T. Choi, S.-K. Yun, I.-J. Yeo, K.-B. Han, T.-S. Kim, and S.-I. Park, A 10b driver IC for a spatial optical modulator for full HDT applications, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers., Feb. 007, pp [6] C.-W. u, A Rail-To-Rail Class-AB Amplifier With an Offset Cancellation for CD Drivers, IEEE J. Solid-State Circuits, vol. 44, no., pp , Feb [7] J.-K. Woo, D.-Y. Shin, D.-K. Jeong, and S. Kim, High-speed 10-bit CD column driver with a split DAC and a class-ab output buffer, IEEE Trans. Consum. Electron., vol. 55, no. 3, pp , Aug [8] Y.-C. Sung, S.-M. So, J.-K. Kim, and O.-K. Kwon, 10bit Source Driver with Resistor-Resistor-String Digital to Analog Converter, SID Symposium Digest 36, pp , 005. [9] Y.-K. Choi, Z.-Y. Wu, K. M. Kim, Y. H. ee, M. S. Cho, H. S. Kim, D. H. ee, W.-G. Jung, A Compact ow-power CDAC Architecture for Mobile TFT-CD Driver ICs, IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 008, pp [10] J.-S. Kang, J.-H. Kim, S.-Y. Kim, J.-Y. Song, O.-K. Kwon, Y.-J. ee, B.-H. Kim, C.-W. Park, K.-S. Kwon, W.-T. Choi, S.-K. Yun, I.-J. Yeo, K.-B. Han, T.-S. Kim, S.-I. Park, 10-bit Driver IC Using 3-bit DAC Embedded Operational Amplifier for Spatial Optical Modulators (SOMs), IEEE J. Solid-State Circuits, vol. 4, no. 1, pp , Dec [11] Y.-J. Jeon, H.-M. ee, S.-W. ee, G.-H. Cho, H. R. Kim, Y.-K. Choi, M. ee, A Piecewise-inear 10b DAC Architecture with Drain- Current Modulation for Compact AMCD Driver ICs, IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 009, pp [1] C.-W. u, P.-Y. Yin, C.-M. Hsiao, and M.-C. F. Chang, A 10b Resistor-Resistor-String DAC with Current Compensation for Compact CD Driver ICs, IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 011, pp