PAPER A Large-Swing High-Driving Low-Power Class-AB Buffer Amplifier with Low Variation of Quiescent Current

Transcription

1 1730 IEICE TRANS. EECTRON., VO.E87 C, NO.10 OCTOBER 2004 PAPER A arge-swing High-Driving ow-power Class-AB Buffer Amplifier with ow Variation of Quiescent Current Chih-en U a, Nonmember SUMMARY A large-swing, high-driving, low-power, class-ab buffer amplifier, which consists of a high-gain input stage and a unity-gain class- AB output stage, with low variation of quiescent current is proposed. The low power consumption and low variation of the quiescent output current are achieved by using a weak-driving and a strong-driving pseudo-source followers. The high-driving capability is mainly provided by the strongdriving pseudo-source follower whose output transistors are turned off in the vicinity of the stable state to reduce the power consumption and the variation of output current, while the quiescent state is maintained by the weak-driving pseudo-source follower. The error amplifiers with sourcecoupled pairs of the same type transistors are merged into a single error amplifier to reduce the area of the buffer and the current consumption. An experimental prototype buffer amplifier implemented in a 0.35-µm CMOS technology demonstrates that the circuit dissipates an average static power consumption of only µ with the standard deviation of only 3.4 µ, which is only 0.874% at a power supply of 3.3 V, and exhibits the slew rates of 2.18 V/µs and 2.50 V/µs for the rising and falling edges, respectively, under a 300 Ω/150 pf load. Both of the second and third harmonic distortions (HD2 and HD3 are 69 db at 20 khz under the same load. key words: large-swing, high-driving, class-ab buffer amplifier, variation of quiescent current, output driver, pseudo-source follower 1. Introduction The class-ab buffer amplifier is widely used for driving heavy resistive or capacitive loads [1] [5]. To achieve the extended voltage swing, the output transistors should be connected in a common-source configuration. The quiescent current of the output transistors should be small, while the dynamic current should be as large as possible. The gates of the two output transistors are normally driven by two in-phase ac signals separated by a dc voltage. For example, Hogervorst et at. [4], [5] proposed a two-stage, compact, power-efficient 3 V CMOS operational amplifier, in which the output stage is biased by a floating class-ab control. angen et at. [6] also proposed compact low-voltage power-efficent operational amplifier cells for VSI, in which a class-ab control is used to bias the output transistors. The above amplifiers are compact and power-efficient. Another approach, which employs a pseudo source follower shown in Fig. 1 to realize class-ab CMOS buffer amplifiers, have been widely used for a large voltage swing output. It is composed of a pair of complementary commonsource transistors with two feedback loops consisting of a Manuscript received January 5, Manuscript revised May 26, The author is with the Department of Electrical Engineering, National Chi Nan University, Taiwan, R.O.C. a cwlu@ncnu.edu.tw This work was supported by the National Science Council of Taiwan, R.O.C., under Contract NSC E Fig. 1 Conventional class-ab buffer amplifier. pair of complementary error amplifiers [7], [8]. This offers a wide output voltage swing and a large ratio between the maximum transient current (class B current and the quiescent current. However, the quiescent current of the output common-source transistors may have a large variation due to the random input-referred offset voltage of the error amplifiers. It varies proportionally with the product of the input-referred offset voltage, the gain of the error amplifier, and the transconductance of the output transistor. Some approaches have been proposed to overcome this problem. Brehmer et at. [8] proposed a feedback circuit inserted in the pseudo source follower to control the dc bias current in the output drivers. Fisher [9] combined a source follower and the pseudo source follower to reduce the variation of the output current. Although the above approaches could alleviate the variation of quiescent current, the additional circuit draws more current and occupies more area. Kih et at. [10] used a low-gain, bias-controlled amplifier as the error amplifier to minimize the variation of the quiescent output current. ith this configuration, an input offsetvoltageof 2mV causes the output quiescent current to change by about 16%. The variation of the quiescent current is reduced but it will be larger for a larger value of input-referred offset voltage. In this work, a large-swing high-driving class-ab buffer amplifier employing two pseudo-source followers is proposed. One of the pseudo-source followers is designed as a weak-driving pseudo-source follower. The other pseudosource follower features a strong-driving capability. In the vicinity of the stable state, only the weak-driving pseudosource follower with small size output transistors is operated to reduce the variation of the quiescent output current. However, in the transient state, the driving capabil-

2 U: A ARGE-SING HIGH-DRIVING O-POER CASS-AB BUFFER AMPIFIER 1731 ity is mainly provided by the strong-driving pseudo-source follower, which has large size output transistors. The quiescent current of the output transistors is independent of supply voltage variations. The additional error amplifiers are merged with the original error amplifiers to reduce the area of the buffer amplifier and the power consumption. The proposed buffer amplifier is designed to work at voice band frequencies for the telecommunication and audio applications. 2. Proposed Class-AB Buffer Amplifier The proposed complete structure of class-ab buffer amplifier, as shown in Fig. 2, consists of a high-gain input stage and a unity-gain class-ab output stage. The input stage is a conventional two-stage amplifier, which is composed of a differential amplifier and a common source amplifier. The unity-gain class-ab output stage employs two pseudo-source followers, in which each pseudo-source follower consists of two complementary error amplifiers and two output transistors. One of the pseudo-source followers is designed as a weak-driving buffer in which the sizes of the output transistors (Mp and Mn are small. The other pseudo-source follower features a strong-driving bufferwith intentionally built-in offset voltages in the error amplifiers and large output transistors (Mp and Mn. The driving capability of the proposed buffer amplifier is mainly provided by this strong-driving pseudo-source follower. However, in the vicinity of the stable state, the output transistors of the strong-driving buffer are turned off, and only the weakdriving pseudo-source follower is active. Then the strongdriving pseudo-source follower will not cause the variation of the quiescent current. The quiescent output current varies only with the product of the input-referred offset voltage, the gain of the error amplifiers, and the transconductance of the output transistors of the weak-driving pseudo-source follower. Since the transconductances of the output transistors (Mp and Mn are reduced, the variation of the output quies- cent current due to the random input-referred offset voltage of the error amplifiers can be greatly reduced. In order to enable the error amplifiers to be operated with input voltages near the negative supply, source-coupled pairs of PMOS transistors are employed to drive the output NMOS transistors (Mn and Mn and vise versa with input voltages near VDD. Although two additional error amplifiers are introduced in the proposed buffer amplifier, the error amplifiers with source-coupled pairs of PMOS transistors are merged into a single error amplifier to reduce the area of the buffer and the current consumption. At the same time, the error amplifiers with NMOS-input transistors are also merged into a single error amplifier. The schematic of the merged source-coupled pair of PMOS transistors with its corresponding output transistors is shown in Fig. 3. The gates of M13 and M14 are connected as the inverting input terminal of the error amplifier, while the gate of M is the noninverting input terminal. The merged source-coupled pair, which is biased by the constant current source, is actively loaded by the current mirror (M15 M17. The aspect ratio of M13 is designed to be the same as that of M, but the / of M14 is chosen to be a little bit smaller than that of M, i.e., = (1 13 = (2 14 In the stable state, the voltage of the noninverting terminal is equal to that of inverting node. The source-to-gate voltages of the source-coupled pairs of PMOS transistors have the same value. Hence, the current flowing in M is equal to that flowing in M13. However, the current in M14 is smaller than that in M due to the smaller transistor size in M14. The currents in M M14 are given as: Fig. 2 Proposed complete structure of class-ab buffer amplifier. Fig. 3 Schematic of the merged source-coupled pair of PMOS transistors with its corresponding output transistors.

3 1732 IEICE TRANS. EECTRON., VO.E87 C, NO.10 OCTOBER 2004 I M = I M13 = I M14 = 3 / [1 / 3 / ] Since the currents in M15 and M16 have the same value, the drain voltage of M16, which is connected to the gate of the weak-driving output transistor Mn, is equal to the gate voltage of M15. The quiescent output current of Mn is then mirrored from I M by a size ratio between Mn and M15, i.e., Mn I Mn = I M (5 M15 Since the differential pair is biased by a constant current source,, the quiescent current of the output transistors is independent of supply voltage variations. The gate voltage of Mn still suffers the offset voltage of the error amplifier. The variation of the output current of Mn, I Mn, can be expressed as: (3 (4 I Mn = V OS g m13 (r o13 //r o16 g m,mn (6 where V OS is the input-referred offset voltage of the error amplifier, g m13 and g m,mn are the transconductances of M13 and Mn, respectively, and r o13 and r o16 are the output resistances of M13 and M16, respectively. However, this variation of the quiescent output current is reduced by choosing a small size of Mn. The current in M is also mirrored to M17. However, the current in M14 is smaller than that in M, so M17 will go out of the saturation region and be in the triode region. The i-v curve, as shown in Fig. 4, depicts the operation of M14 and M17, where the intersection of the two solid lines indicates the drain-to-source voltage of M17 in the stable state. Since M17 is in the triode region, its drain-to-source voltage can be approximately expressed as: Fig. 4 The i-v curves of M14 and M17. The intersection (P1 of the two solid lines indicates the drain-to-source voltage of M17 in the stable state. However, the intersection (P2 represents the same voltage in the transient state. I M14 V DS,M17 ( µ n C OX (/ 17 VGS,M17 V tn < V tn + V OS g m14 (r o14 //r o17 (7 where 2I M V GS,M17 = V GS,M15 = µ n C OX 15 + V tn, (8 g m14 is the transconductance of M14, and r o14 and r o17 are the output resistances of M14 and M17, respectively. In order to reduce the static power consumption and the variation of the output quiescent current due to the random offset voltage in the error amplifier, the strong-driving output transistor Mn is designed to be in the cut off region. Therefore the drain voltage of M17, which is connected to the gate of Mn, should be smaller than the value of V tn + V OS g m14 (r o14 //r o17. This can be achieved by decreasing the aspect ratio of M14 or/and increasing the size of M17. hen the voltage of the inverting terminal is increased, the drain voltages of M16 and M17 are reduced. The output transistor Mn is still cut off from the output node. However, when the voltage of the inverting terminal is reduced, say, by a step voltage V 1, the currents in M M14 are given as: V SG13 = V SG14 = V SG + V (9 I M = 1 2 µ ( pc OX VSG Vtp 2 (10 I M13 = 1 2 µ ( pc OX VSG13 Vtp 2 (11 I M14 = 1 2 µ pc OX 1 ( ( VSG14 Vtp 2 ( I M + I M13 + I M14 = (13 The currents in M M14 then can be obtained from Eqs. (9 (13. That is: I M = 3 ( [ 2 V + 2 ( ] (14 V SG V tp 2 V (1 + V SG V tp I M13 = 3 ( [ 2 V + 2 ( ] (15 V SG V tp I M14 = (1 + 2 V V SG V tp V V SG V tp [ 1 ( ] [ 2 ] (16 They can be seen that the current in M is reduced, and the currents in M13 and M14 are increased from the stable state. The current in M is mirrored to M17. As a result, M17 will go into the saturation region. The dashed lines of the i-v curves shown in Fig. 4 show the transient operation of M17. The intersection of the lines is moved from P1 to P2. This

4 U: A ARGE-SING HIGH-DRIVING O-POER CASS-AB BUFFER AMPIFIER 1733 Fig. 5 The complete circuit schematic of the proposed class-ab buffer amplifier. shows that the drain voltage of M17 will increase to turn on the strong-driving output transistor Mn.ThenMn starts to discharge the output node. Due to the negative feedback of the buffer amplifier, the drain voltage of M17 would come back to its stable voltage. hen the drain voltage of M17 is reduced to the level of V tn ± V OS g m14 (r o14 //r o17,mn stops discharging the output node. In this way, the discharge capability of the unity-gain class-ab output stage is mainly provided by the strong-driving output transistor Mn,butthe variation of the output quiescent current is greatly reduced. The merged error amplifier with source-coupled pairs of NMOS transistors works in a similar way as do the merged error amplifier with source-coupled pairs of PMOS transistors. The strong-driving output transistor Mp provides a large charge capability but it is cut off and does not consume any power in the quiescent state. Figure 5 shows the complete circuit schematic of the proposed buffer amplifier where M1 M10 are the high-gain input stage, M11 M17 are the merged error amplifier with source-coupled pair of PMOS transistors, M18 M27 are the merged error amplifier with source-coupled pair of NMOS transistors, Mn, Mp, Mn and Mp are the output driving transistors, and M28 M37 and Ccs1 Ccs5 are for the frequency compensation. The aspect ratios of the transistors and the values of the capacitors are summarized in Table 1. In the error amplifiers, due to the built-in offset voltages, the output transistors of the strong-driving pseudo source follower are cut off every signal period. This deteriorates the crossover distortion characteristics. However, the negative feedback of the pseudo source follower reduces the harmonic distortion by an amount related to the loop gain [11] [13]. Also, The distortion generated by the strongdriving pseudo source follower will be suppressed by the internal feedback loops formed by the compensation capacitors, C cs2 and C cs5 [13]. Hence, the harmonic distortion due Table 1 Device sizes ([µm/µm] for transistors. to the built-in offset voltages is greatly reduced. Figure 6 shows the simulated harmonic distortion of the proposed amplifier, which is connected as a unity-gain buffer under a 300 Ω/150 pf load with a 2.4 V input swing for a 3.3 V supply voltage. The square, rhombus, and triangle lines are for the harmonic distortions HD2, HD3, and THD, respectively. It can be seen that the input-referred built-in offset voltage will not greatly deteriorate the distortion characteristics. The built-in offset voltage is generated from the mismatch design of the error amplifiers (A 1 and A 2. In this work, a mismatch value of 1 µm between M and M14 (also M22 and M24 is used to implement this amplifier. This value of size mismatch generates an input-referred offset voltage of 0.7 mv. This small input-referred built-in offset voltage,

5 1734 IEICE TRANS. EECTRON., VO.E87 C, NO.10 OCTOBER 2004 Fig. 7 The die photograph of the proposed buffer amplifier. Fig. 6 The simulated harmonic distortion of the proposed amplifier, which is connected as a unity-gain buffer under a 300 Ω/150 pf load with a 2.4 V input swing for a 3.3 V supply voltage. which will be amplified by the error amplifier, is enough to turn off the large output transistors (Mp and Mn inthestable state. Hence, the intentionally built-in offset voltages in the error amplifiers will hardly affect the distortion and the proposed amplifier is suitable for continuous-time applications. 3. Experimental Results The proposed output buffer amplifier was fabricated using a 0.35-µm CMOS technology. The die photograph is shown in Fig. 7. The active area of the buffer is only µm 2. Figure 8 shows the measured dc transfer characteristic of the proposed buffer amplifier connected in a unity-gain configuration at a single power supply of 3.3 V with different resistive loads. The voltage swing is V under a 300 Ω resistive load. The average value of the measured offset voltages is 0.7 mv and the standard deviation is 0.7 mv. The quiescent currents of 8 chips, which are measured under a 300 Ω resistive load, are summarized in Table 2. For these 8 samples, the mean value of the quiescent current is 117.8µA, which is smaller than those of [4] [6], [8] [10], and the standard deviation is only 1.03 µa. They feature a mean value of the static power consumption of µ and a standard deviation of 3.4 µ, which is only 0.874% of the mean value. These values are low as compared with those of [10]. The class-ab behaviour is measured and shown in Fig. 9 where the maximum signal current that can be delivered to the load is 36.6 ma but the quiescent current is only 14 µa. The ratio between the maximum signal current and the quiescent current is 2614, which is much larger than those of the amplifiers [8], [10]. Figure 10 shows the measured result of the output with the input of 2.4 V swing of a 50 khz triangular wave of the unity-gain buffer amplifier loaded with 300 Ω resistor in parallel with a 150 pf capacitor. It can be seen that the output basically follows the input. The step responses of the unity-gain buffer amplifier with the same load with the voltage swings of 20 mv Fig. 8 The measured dc transfer characteristic of the proposed buffer amplifier connected in a unity-gain configuration at a single power supply of 3.3 V with different resistive loads. Table 2 Quiescent currents of 8 chips. [µa] Fig. 9 The measured class-ab behaviour of the proposed buffer amplifier.

6 U: A ARGE-SING HIGH-DRIVING O-POER CASS-AB BUFFER AMPIFIER 1735 Fig. 10 The measured result of the output with the input of 2.4 V swing of a 50 khz triangular wave of the unity-gain buffer amplifier loaded with 300 Ω resistor in parallel with a 150 pf capacitor. Fig. 13 The measured results of the output with the input of a large dynamic range (2.4 V pp of a 20 khz sinusoidal wave for the unity-gain buffer amplifier. Fig. 11 The measured step response of the unity-gain buffer amplifier loaded with 300 Ω resistor in parallel with a 150 pf capacitor with the voltage swing of 20 mv. Fig. 14 The measured magnitude spectrum of the proposed buffer amplifier with a 2.4 V pp output swing into a 300 Ω/150 pf load. and 2.4 V are shown in Figs. 11 and, in which Fig. 11 shows the small signal response with 20 mvpp and Fig. shows the large signal response with 2.4 V pp.theslewrates are 2.18 V/µs and 2.50 V/µs for the rising and falling edges, respectively. Figure 13 shows the measured results of the output with the input of a large dynamic range (2.4 V pp of a 20 khz sinusoidal wave for the unity-gain buffer amplifier. Figure 14 shows its magnitude spectrum of the proposed buffer amplifier with a 2.4 V pp output swing into a 300 Ω/150 pf load. Both of the second and third harmonic distortions (HD2 and HD3 are 69 db at 20 khz under the same load. All of the measured results are summarized in Table Conclusions Fig. The measured step response of the unity-gain buffer amplifier loaded with 300 Ω resistor in parallel with a 150 pf capacitor with the voltage swing of 2.4 V. A large-swing, high-driving, low-power, class-ab buffer amplifier, which employs two pseudo-source followers, with low variation of quiescent current has been presented. The

7 1736 IEICE TRANS. EECTRON., VO.E87 C, NO.10 OCTOBER 2004 Table 3 Performance summary. strong-driving pseudo-source follower mainly provides the driving capability during the transient but its output transistors are turned off in the vicinity of the stable state to reduce the power consumption and the variation of the quiescent output current. An experimental prototype buffer amplifier implemented in a 0.35-µm CMOS technology demonstrates that the circuit dissipates an average static power consumption of only µ with the standard deviation of only 3.4 µ, which is only 0.874% at a power supply of 3.3 V, and exhibits the slew rates of 2.18 V/µs and 2.50 V/µsforthe rising and falling edges, respectively, under a 300Ω/150 pf load. Both of the second and third harmonic distortions (HD2 and HD3 are 69 db at 20 khz under the same load. Acknowledgments The author would like to thank National Chip Implementation Center (CIC for chip fabrication. This work was supported by the National Science Council, Republic of China, under Grant NSC E References [1] C.-. u and C.. ee, A low power high speed class-ab buffer amplifier for flat panel display application, IEEE Trans. Very arge Scale Integr. (VSI Syst., vol.10, no.2, pp , April [2] C.-. u, A low power high speed class-ab buffer amplifier for flat panel display driver application, Digest of SID, pp , [3] F. You, S.H.K. Embabi, and E. Sanchez-Sinencio, ow-voltage class AB output amplifiers with quiescent current control, IEEE J. Solid-State Circuits, vol.33, no.6, pp , June [4] R. Hogervorst, J.P. Tero, R.G.H. Eschauzier, and J.H. Huijsing, A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VSI cell libraries, IEEE ISSCC, pp , [5] R. Hogervorst, J.P. Tero, R.G.H. Eschauzier, and J.H. Huijsing, A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VSI cell libraries, IEEE J. Solid-State Circuits, vol.29, no., pp , Dec [6] K.-J. de angen and J.H. Huijsing, Compact low-voltage powerefficient operational amplifiers cells for VSI, IEEE J. Solid-State Circuits, vol.33, no.10, pp , Oct [7] A. Torralba, R.G. Carvajal, J. Martinez-Heredia, and J. Ramirez- Angulo, Class AB output stage for low voltage CMOS op-amps with accurate quiescent current control, Electron. ett., vol.36, no.21, pp , Oct

8 U: A ARGE-SING HIGH-DRIVING O-POER CASS-AB BUFFER AMPIFIER 1737 [8] K.E. Brehmer and J.B. ieser, arge swing CMOS power amplifier IEEE J. Solid-State Circuits, vol.sc-18, no.6, pp , Dec [9] J.A. Fisher, A high-performance CMOS power amplifier, IEEE J. Solid-State Circuits, vol.sc-20, no.6, pp.00 05, Dec [10] J. Kih, B. Chang, D.-K. Jeong, and. Kim, Class-AB large-swing CMOS buffer amplifier with controlled bias current, IEEE J. Solid- State Circuits, vol.28, no., pp , Dec [11] G. Palumbo and S. Pennisi, High-frequency harmonic distortion in feedback amplifiers: Analysis and applications, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol.50, no.3, pp , March [] P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, 3rd ed., iley, New York, [13] F.N.. Op t Eynde, P.F.M. Ampe,. Verdeyen, and.m.c. Sansen, A CMOS large-swing low-distortion three-stage class AB power amplifier, IEEE J. Solid-State Circuits, vol.25, no.1, pp , Feb Chih-en u was born in Tainan, Taiwan, R.O.C., on October 11, He received the B.S. degree in Electronic Engineering from National Twiwan Institute of Technology, Taipei, in 1991, the M.S. degree in Electro-optics from National Chiao Tung University, Hsinchu, Taiwan, in 1994, and the Ph.D. degree in Electronic Engineering from National Chiao Tung University. During , he was an Assistant Professor of the Department of Electrical Engineering, Da-yeh University. He joined the National Chi Nan University, Puli, Nan-Tou, Taiwan, in 2001 and is currently an Assistant Professor in the Department of Electrical Engineering. His research interests include low-power analog design, CD driver design, and analog/mixed-mode IC design.