ECE2274 Pre-Lab for MOSFET logic LTspice NAND Gate, NOR Gate, and CMOS Inverter

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1 ECE2274 Pre-Lab for MOFET logic LTspice NAN ate, NOR ate, and CMO Inverter 1. NMO NAN ate Use Vdd = 9.. For the NMO NAN gate shown below gate, using the 2N7000 MOFET LTspice model such that Vto = 2.0. The input logic 1 = 9 volt and ground as a logic 0. Make a truth table showing the four possible combinations of Vin1 and Vin2 and the outputs. Choose Rd (drain current limit resistor) such that the drain currents of the NMO devices will be about 30mA when the is in a low state. Then run a C.OP Bias Point simulation (use the added 2N7000 model in LTspice) on your design with the four possible input combinations for Vin1 and Vin2 to verify your gate. Observe the output voltage value for each input combination. Print your circuit schematic showing voltages for all four input combination. Vdd Rd Vin1 Q1 NMO Vin2 Q2 NMO Nmos NAN ATE 2. NMO NOR ate Use Vdd = 9.. esign an NMO NOR gate using the 2N7000 MOFET the model has Vto = 2.0. Limit the drain current total to 30mA with a drain resistor (Rd). how all work for your design and drawing. Then simulate your design in LTspice with C.OP Bias Point simulations as you did for the NAN gate. Print out your circuit schematic showing voltages for all four input combination add from the view menu node voltage and drian current to display on the schematic. Also, fill in the truth table with all of the C.OP Bias Point simulation voltage values. Page 1 of 6

2 3. CMO Inverter Use V = 9.. esign a CMO inverter using a NMO and PMO FET. The drain current will be limited by the two external Ω source resistors (Rnmos, Rpmos). The MOFETs that we use in the lab both have a V threshold voltage of about 2.0V and internal resistance is R = 0.2Ω. Assume that there is a input voltage level 2.0V < Vin < V 2.0V that will turn on both FETs at the same time. This will cause a large current flow that could damage the two devices. Because there is period of time when both devices on we will use a 1kHz triangle waveform as input so the time the devise send in a high current state will short in LTspice. (Triangle Wave) Use LTspice to plot the input triangle waveform (PULE) 0 to 9v, output voltage waveform, and the current thru the devices. (C sweep) Plot CMO Transfer characteristic curve use C sweep Vin from 0V to 9V. Plot vs Vin mark on plot V OH, V OL, V IL and V IH. V V in (Triangle Wave) set PULE V in (C weep) Q1 PMO Q2 NMO 1kHz amplitude 0v to 9v Triangle wave PULE 0V, 9V Tr=0.5ms Tf=0.5ms Tper=1ms, Td=0, Ton =1ns 0V to 9V 200mv step LTspice (TP0606) Lab (TP0606) LTspice (2N7000) Lab (2N7000) LTspice TP0606 PMO Internal resistance LTspice 2N7000 NMO Internal resistance Vto=-2 volts R =0.2 ohms Vto = 2 volts R = 0.2 ohms Page 2 of 6

3 Vin.dc Vin include 2N7000.sub.include TP0606.sub Rin Rpmos TP0606 M1 Vdd 9V 10k Vin 0 Rser=50 M2 2N7000 Rnmos Rload 10k CMO inverter for LTspice Cmos Transfer characteristic curve. Required Attachments: NAN Truth table Four schematics with voltages and currents of nodes and branches NOR Truth table Four schematics with voltages and currents of nodes and branches 5. Cmos Transfer characteristic curve (Triangle Wave), (C sweep) 2 plots Page 3 of 6

4 Laboratory Exercise MOFET logic NAN ATE, NOR ATE, and CMO inverter 1. You must test your 2N7000 NMO with the curve tracer before build your experiment. et curve trace to N-FET, Is Max = 10ma, Vds max =10V, Vg/step = 0.1V, Offset = 1.8V, Rload = 10, N teps = You must test your TP0606 PMO with the curve tracer before build your experiment. et curve trace to P-FET, Is Max = 10ma, Vds max =10V, Vg/step = 0.1V, Offset = - 1.8V, Rload = 10, N teps = Build the NAN gate. Measure the output voltage levels with 10k load resistor connected to ground. You will use the voltmeter to verify the NAN gate s operation. Try all of the input combinations. 4. Build the NOR gate that you designed in the Pre-Lab. Use V = 9. Again, use an 10k load resistor connected to ground to determine the output states. Verify the truth table for a NOR gate. 5. Build CMO Inverter with both the external Ω source resistors to limit the current. C sweep the input from 0V to 9V in 200mv steps to plot the Cmos inverter (10k load resistor) transfer characteristic curve, print the plot and mark the V OH, V OL, V IL and V IH Page 4 of 6

5 ATA HEET ATA HEET MOFET logic Name: Name: Instructor: Class day and time: ate: Bench number: NAN ATE, NOR ATE, and COM Inverter 1. NAN ATE static test. Vdd = Vin1 Vin2 2. NOR ATE static test. Vdd = Vin1 Vin2 Page 5 of 6

6 3. CMO Inverter V current limit PMO Q1 Vin 10K Rin Q2 NMO 10K Rload hunt and current limit Table CMO inverter static test. Vdd = Vin 0v 9v From C sweep of CMO inverter to Vin Mark on plot, include the plot. Name Voltage VOH VOL VIL VIH Page 6 of 6

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