Processor Power and Power Reduction

Transcription

1 EE-382M VLSI II Processor Power and Power Reduction Byron Krauter EE 382M Class Notes Foil # 1

2 Outline Power s Importance Why power matters even for desktop processors Power Estimation Active Power Leakage Power Power Reduction Design options for keeping power under control Early Design Planning for Power EE 382M Class Notes Foil # 2

3 Power s Importance EE 382M Class Notes Foil # 3

4 Power = Package Pentium 4 die is about 1.5g and less than 1cm^3. Pentium-4 in package with interposer, heat sink, and fan can be 500g and 150cm^3. Fan Heat Sink Integrated Heat Spreader Decoupling Capacitors Interposer Processor Processor Pins OLGA Pins Package Pins Modern processor packaging is complex and adds significantly to product cost. EE 382M Class Notes Foil # 4

5 Power = Pins Each Vcc or Vss pin can only carry 0.5-1W of power. Pentium-4 uses 423 pins of which 223 are Vcc or Vss. Increased power requires more package pins More pins make package more expensive New package development is costly Motherboard redesign slows product acceptance EE 382M Class Notes Foil # 5

6 Power = Heat Operating temperature is determined by package, heat sink, and chip power. Rthermal Cost ( C/W) ($) Al Heat Sink Cu Heat Sink Vapor Chamber Liquid Cooling Refrigeration Typical package adds another 0.25 C/W. Tj = Rthermal*Power + Tambient Increased power requires better heat sink or higher operating temperature Heat sink adds to packaging costs Higher temperature degrades performance (about 2% per 5 C), increases leakage power, and reduces reliability EE 382M Class Notes Foil # 6

7 Power = Wire Tracks Vcc Vss Vcc At all metal layers 20-40% of wire tracks are used by Vcc and Vss. Vss Vcc Increased power requires denser power grid Power lines reduce wire tracks available for signals EE 382M Class Notes Foil # 7

8 Power = Power Supply Tolerance Power supply tolerances are determined by chip, package, and multi-cycle power fluctuations Package Quiet Circuits & Added Caps Background Power & Leakage Switching Circuits Z(f) f = (2π * (LC) 1/2 ) amp saturated ramp τ r = 2.5, 5.0, & 10 nsec frequency EE 382M Class Notes Foil # 8

9 Power = Battery Life Improved battery & processor designs have increased laptop mobility A 1kg NiCad battery (~50 Wh/kg) would power a Pentium 4 (~80 W) alone for less than 1 hour. A 1kg Li-ion battery (~120 Wh/kg) will now power Pentium M (~30 W) laptop up to three hours However, increased power reduces battery life span Li-ion batteries lose 20% capacity/year at 25 C and losses increase with temperature Processor power can add significantly to space, weight, and heat of portables Requiring a system fan adds more to space and weight. EE 382M Class Notes Foil # 9

10 Power = Performance Processor performance is affected by power High chip temperatures degrade circuit performance Large across-chip chip temperature re variations introduce clock skew High chip power limits use of high-performance circuits Power transients determine minimum power supply voltage EE 382M Class Notes Foil # 10

11 Power Estimation EE 382M Class Notes Foil # 11

12 Power Components Active Power Produced by switching activity Strongly affected by application and clock gating S/D Leakage Subthreshold current Strongly affected by use of low Vt and stack effect Gate Leakage Gate oxide tunneling current Strongly affected by oxide thickness EE 382M Class Notes Foil # 12

13 Active Power P active = 1/ 2 AF SF Cswitch den Area V 2 freq AF = unit activity it factor SF = circuit switching factor within a unit Cswitch-den = switching capacitance density Area = die area Vcc = supply voltage freq = clock frequency Active power can be increased 10-20% by short circuit current. For current high performance processors, active power is >60% of total power, and the largest fraction is active clock power! EE 382M Class Notes Foil # 13

14 Activity Factor vs Switching Factor This course expresses total switching probability as a product of two terms Total Switching Probability = AF * SF where AF = Activity factor = probability a unit is active SF = Switching factor = average number of times a circuit node switches each clock cycle AF ranges from 0 to 1 Cannot use a unit more than 100% of the time SF ranges from 0 to N where e N > 1 Logic nodes can switch more than once due to glitches But average logic switching factor is low (e.g ) Clocks always switch twice a cycle! EE 382M Class Notes Foil # 14

15 Why ½ CV 2 f Consider small toggling inverter driving a big capacitor T cycle EE 382M Class Notes Foil # 15

16 Why ½ CV 2 f - PFET charges capacitor from the supply when input falls T cycle charge Power supply delivers charge Q = CV Energy delivered by supply = QV = CV 2 ½isdissipated&½isstored ½ stored EE 382M Class Notes Foil # 16

17 Why ½ CV 2 f - NFET discharges capacitor locally T cycle discharge NFET locally dissipates stored energy = ½ CV 2 Energy QV = CV 2 is delivered by supply over two cycles! Power = (CV 2 )/2*T cycle = ½CV 2 f EE 382M Class Notes Foil # 17

18 Reducing Active Clock Power Active clock power is still largest power component Idle unit clock power is wasted power Reduction techniques es Clock gating Addresses idle unit power Increases power supply noise Pulse latches ~50% local clock power reduction (over Master/Slave clocking) Fast path exposure Multiple threads Better memory utilization Multiple cores With shallower pipelines running at slower frequencies EE 382M Class Notes Foil # 18

19 Activity Factor 40 Activity factor is a strong function of the application. enchmarks Number of B % 25% 50% 75% 100% Power as a Percent of Max Power Packaging designed to support only typical power. Thermal sensor on-chip halves clock frequency if chip becomes too hot. Max Power = maximum power any application could dissipate Thermal Design Point (TDP) Power = power used by typical application. EE 382M Class Notes Foil # 19

20 Activity Factor Activity factor is also strongly affected by block function. Unit Unit Activity MacroInstr Translation 0.1 Floating Point Unit 0.2 Integer Execution Unit 0.5 Uop Checker 0.7 Can be estimated using performance or RTL models. EE 382M Class Notes Foil # 20

21 Cswitch-den Process generation determines average Cswitch density. 150 Scaling of Cswitch Density Cswitch (pf F/mm^2) Cswitch density increases by x1.35 per process generation 0 Pentium Pro 0.50um Pentium II 0.35um Pentium III 0.25um Pentium III 0.18um EE 382M Class Notes Foil # 21

22 Cswitch-den Circuit style can greatly affect Cswitch density of a block. 0.18um Circuit Type Cswitch-den (pf/mm^2) Domino 300 Static 100 Large-Signal Array 50 Small-Signal Array 20 P active = 1/ 2 SF C switch den Area V 2 freq EE 382M Class Notes Foil # 22

23 Short Circuit Current Non-zero input rise time temporarily shorts Vdd & Gnd through the devices I sc EE 382M Class Notes Foil # 23

24 Subthreshold Leakage log(ids) Subthreshold Slope For Vgs<Vt, drain to source current is not actually zero. ( Vgs Vt) q nkt d e 1 e I ds 1 qvds kt Vds=Vcc kt q = 100 C Vt Vgs(V) Slope mv/decade Reductions in Vt have greatly increased leakage currents with each generation. EE 382M Class Notes Foil # 24

25 Subthreshold Leakage & Scaling For circuit operation Vt still set at approximately 20% Vcc And subthreshold characteristics haven t changed: Ids(Vgs=Vt) 50 namp/square & subthreshold slope 80 mv/ decade Ids (A) 10-7 Vcc = 1 Volt I on /I off /0.08 Vcc = 5 Volt 10-8 I on/i off / Vds=VccV Vgs (V) EE 382M Class Notes Foil # 25

26 Subthreshold Leakage & Stack Effect 0 0 N1 I ds e q ( Vgs Vt ) nkt 1 Vt( Vds ) V t( Vd = Vs = 0 e qvds kt Body Effect DIBL ) + λ 1Vs λ 2V ds Vx N2 ~10x less leakage than inverter! EE 382M Class Notes Foil # 26

27 Gate Leakage N+ e- N+ N+ Electron s position is not well defined and for oxides less than 5nm thick, tunneling current through the oxide can be significant. Gate leakage is only significant in devices in the linear or saturation regime. Reductions in Tox have greatly increased leakage currents with each generation. EE 382M Class Notes Foil # 27

28 Estimating Leakage Power S/D Leakage Pwr = Vcc*Area*TranWidthPerArea*StackEffect*AvgLeak AvgLeak = (% HighVt)*(HighVt Leak) + (% LowVt)*(LowVt Leak) TranWidthPerArea = 0.2m/mm^2 (for 0.18um process) StackEffect = 0.35 Gate Leakage Pwr = Vcc*Area*TranWidthPerArea*PercentOn*GateLeak TranWidthPerArea = 0.2m/mm^2 (for 0.18um process) PercentOn = 0.5 EE 382M Class Notes Foil # 28

29 Power Reduction EE 382M Class Notes Foil # 29

30 Choose low power circuit styles To reduce power and design time use of phased based static ti and domino circuits it must be kept to a minimum. i Circuit Type Pentium 4 (% of core) Static-Flops 45% L-Sig-Array 25% Static-Latches 15% Domino 15% EE 382M Class Notes Foil # 30

31 Clock Gating Every Local Clock Buffer should have an enable signal. Addr3 Addr2 Addr1 Addr0 Dec Wordline Wordline Driver Wordline Driver Wordline Driver RdEn Wordline Driver Bank Gclk EE 382M Class Notes Foil # 31

32 Clock Gating Performing logic function with clock enables makes clock gating even more effective. Addr3 Addr2 Addr1 Dec Wordline RdEn Addr0# RdEn Addr0 Wordline Driver Wordline Driver Wordline Driver Wordline Driver Bank Gclk Watch out for logic bugs and creating speedpaths. EE 382M Class Notes Foil # 32

33 Move Flip-Flops to Narrow Points in Logic Cone MSFF MSFF MSFF MSFF Logic Cone Logic Cone ClkA ClkB ClkA ClkB Total number of sequentials can be dramatically affected by what portion of the logic cone is captured. EE 382M Class Notes Foil # 33

34 Limit Use of Low Vt Typical targets are 10-25% of total device width to be low Vt. When adding low Vt devices to the critical path look for Narrow points in logic cone Gates with small device widths Series rather than parallel stacks EE 382M Class Notes Foil # 34

35 Thermal Throttling Benchmark A Relative Performance e 100% 90% 80% System #1 System #2 System #3 System #4 70% External Ambient Temperature Slowing processor based on temperature allows packaging to be designed for typical power instead of maximum power. EE 382M Class Notes Foil # 35

36 Thermal Throttling Without CPU clock reduction Insert idle states Clockgateidle units With CPU clock reduction Dynamic frequency scaling Dynamic power decreases by f Creates additional asynchronous boundaries Dynamic voltage & frequency scaling Simultaneously decrease both voltage & frequency Bigger power savings Dynamic power (within core) decreases by V 3 Energy V 2 & frequency V Static power drops exponentially Does not necessarily reduce system energy/task EE 382M Class Notes Foil # 36

37 Global Power Reduction Some power reduction techniques must be applied at the fullchip level: Thermal throttling Reduces cost because package & cooling designed for typical power instead of max power Multiple supply voltages Only run performance critical circuits at high voltage Sleep transistors Switch off power to sections of the chip during idle EE 382M Class Notes Foil # 37

38 Low Power vs. High Performance Design Circuits & design techniques are similar Circa 1995, Alpha team ( MHz) team designed ARM V4 (0.5 Watt at 160 MHz)* Reported tradeoffs going from 26 to 0.5 Watts Change Reduction Power Vdd reduction 5.3x 4.9 W Reduce functions 3x 1.6 W Scale process 2x 0.8 W Reduce clock load 1.3x 0.6 W Reduce clock rate 1.25x 0.5 W * Montonaro et al, A 160MHz, 32b, 0.5W CMOS RISC Microprocessor, IEEE Journal Solid-State Circuits, vol. 31, no. 11, Nov EE 382M Class Notes Foil # 38

39 Lower Average Device Width Leakage and active power reduced by lowering average device width. Use AOI gates Replace multiple fast gates with one small AOI gate Skew P/N ratios Don t speed up both transitions when only one is failing timing i Use Low Vt to stay static Increase in leakage can be less than increase in active power if domino used Size down gates on paths with positive maxdelay margin CAD tools exist to do this automatically EE 382M Class Notes Foil # 39

40 Sleep Transistor Leakage Reduction Large transistors t added d between ground and virtual ground Turned off to eliminate all unit power But logic states are lost Biased for low conduction to create non-zero virtual ground Leakage is reduced via stack effect Logic states are preserved Used in Xeon arrays for leakage control (2006 ISSCC) Unit or Array virtual ground biased for leakage reduction functional enable sleep enable EE 382M Class Notes Foil # 40

41 Early Design Planning for Power EE 382M Class Notes Foil # 41

42 Early Design Planning for Power EDP for power is important because power affects Cost Packaging, cooling, Performance Power supply tolerance Circuit it selection Battery life Schedule Chip area, wiring resources, Reliability Setting & meeting initial schedule, cost, and performance goals requires EDP for power EE 382M Class Notes Foil # 42

43 Early Design Planning for Power EDP for power consists of four tasks Early simulation of major power dissipation components Early quantification of chip power Total chip power Maximum power density Total chip power fluctuations ti inherent & added fluctuations due to clock gating Early power distribution analysis (dc, ac, & multi-cycle) Early allocation & coordination of chip resources Wiring tracks for power grid Low Vt devices Dynamic circuits Clock gating Placement & quantity of added decoupling capacitors EE 382M Class Notes Foil # 43

44 Early Design Planning for Power Significant power dissipation components include Global clock distribution (Watts) Clock regenerators & latches (mw/latch) Dynamic circuits (mw/circuit) Low Vt device leakage (mw/micron) Array design & organization Power distribution analysis includes DC drop & electromigration ( average power) Single cycle drops ( maximum power in cycle) Multi-cycle drops ( multi-cycle fluctuations) EE 382M Class Notes Foil # 44

45 Summary EE 382M Class Notes Foil # 45

46 Summary Power is critical even for desktop processors To estimate power designer needs: Process Data Vcc and frequency Unit or fub activity factor Fub area, circuit type, and percent low Vt Designer s choices can dramatically affect power Low power circuit styles & clock gating are most important Setting/meeting initial schedule, performance, & cost goals requires EDP for power EE 382M Class Notes Foil # 46

47 Bibliography EE 382M Class Notes Foil # 47

48 Power References A. Chandrakasan, et. al., Low Power CMOS Digital Design", IEEE Journal of Solid State Circuits, pp , Good general discussion of sources of power and design options. Z. Chen, et. al., 0.18um Dual Vt MOSFET Process and Energy-Delay Measurement", International Electronic Devices Meeting, pp , Selects threshold voltage based on minimizing energy-delay product. T. Fletcher, Microprocessor Technology Trends", International Electronic Devices Meeting, pp , rather Predicts power will become limiting factor for processor frequency than device constraints. N. Jouppi, et. al., Designing, Packaging, and Testing a 300MHz 115W ECL Microprocessor", IEEE Micro, pp , chip. Great discussion of tradeoffs in packaging an extremely high power They use a 6 inch high thermosiphon. EE 382M Class Notes Foil # 48