Disseny físic. Disseny en Standard Cells. Enric Pastor Rosa M. Badia Ramon Canal DM Tardor DM, Tardor

Transcription

1 Disseny físic Disseny en Standard Cells Enric Pastor Rosa M. Badia Ramon Canal DM Tardor 2005 DM, Tardor

2 Design domains (Gajski) Structural Processor, memory ALU, registers Cell Device, gate Transistor Program State machine Module Boolean equation Transfer function Behavioral Masks Gate Functional unit Macro IC Physical / Geometric DM, Tardor

3 Abstraction levels and synthesis Architectural level Logic level Circuit level Layout level Behavioral level For I=0 to I=15 Sum = Sum + array[i] 0 State Architecture synthesis Logic synthesis Circuit synthesis Layout synthesis Structural level Memory Control + (register level) Clk (Library) Silicon compilation (not a big success) DM, Tardor

4 Design domains (Gajski) System level Algorithmic RT level Logic Circuit DM, Tardor

5 Design domains (Gajski i Kuhn) Structural Processor, memory ALU, registers Cell Device, gate Transistor System level Algorithmic RT level Logic Circuit Program State machine Module Boolean equation Transfer function Behavioral Masks Gate Functional unit Macro IC Physical / Geometric DM, Tardor

6 Design domains (Gajski i Kuhn) Structural Processor, memory ALU, registers Cell Device, gate Transistor System level Algorithmic RT level Logic Circuit Program Algorithm Module Boolean equation Transfer function Behavioral Descripció textual Masks Gate Functional unit Macro IC Physical / Geometric DM, Tardor

7 Typical Design Path Behavioral Structural System Chip RT level Text Algorithmic Data flow Gate Circuit Physical design Logic Transitors Geometrical layout DM, Tardor

8 VLSI Design Cycle System Specification Circuit Design Architectural Design Physical Design Functional Design Fabrication Logic Design Packaging DM, Tardor

9 VLSI Design Cycle System Specification Circuit Design Architectural Design Physical Design Functional Design Fabrication Logic Design Packaging DM, Tardor

10 Physical Design Cycle Circuit Partitioning Floorplanning & Placement Routing Layout Compaction Extraction and Verification DM, Tardor

11 Physical Design Cycle Circuit Partitioning Partition a large circuit into sub-circuits (called blocks). Factors like #blocks, interconnections between blocks, are considered DM, Tardor

12 Physical Design Cycle Floorplanning Set up a plan for a good layout. Place the blocks at an early stage when details like shape, area, positions of I/O pin, are not yet fixed. Deadspace DM, Tardor

13 Floorplanning Blocks are placed in order to minimize area and the connections between them. DM, Tardor

14 Physical Design Cycle Placement Exact placement of the modules (modules can be gates, standard cells, ). Details of the design are known and the goal is to minimize the total area and interconnect cost. v Feedthrough Standard cell type 1 Standard cell type 2 DM, Tardor

15 Channel definitions Blocks are placed so empty rectangular spaces are left between them. These spaces will be later used to make the interconnection. DM, Tardor

16 Physical Design Cycle Routing Complete the interconnections between the modules. Factors like critical path, wire spacing, are considered. Include global routing and detailed routing. Feedthrough Standard cell type 1 Standard cell type 2 DM, Tardor

17 Global Routing Each connection will go from each origin block, through the channels until the end block. DM, Tardor

18 Global Routing The length of the connections will depend on the situation of the blocks rather than the way the routing is done. DM, Tardor

19 Detailed Routing The space required for each channel will depend on the complexity and density of the connections. DM, Tardor

20 Detailed Routing Aligned connections require a smaller channel (similar to that of a bus). DM, Tardor

21 Detailed Routing Non-aligned connections increment the complexity of the routing and it increases the amount of space required. DM, Tardor

22 Detailed Routing The number of crossings determines the space required. The size of the channel may have to be increased. DM, Tardor

23 Detailed Routing Aligned connections reduce dramaticaly the area required of the channel for completing the routing. DM, Tardor

24 Bus area The area of each bus is proportional to the number of bits of the bus. DM, Tardor

25 Bus area Los giros deben realizarse al estilo Manhattan, lo cual aumenta el área requerida. DM, Tardor

26 Bus cross-coupling The bits in a bus can interfere negatively between them: cross-coupling. DM, Tardor

27 Bus cross-coupling Los distintos bits en un bus pueden interaccionar entre ellos deforma negativa: cross-coupling. DM, Tardor

28 Bus cross-coupling If this is the case, the victim must be protected using any isolating technique (e.g. increasing the separation). DM, Tardor

29 Bus cross-coupling Another solution is to use differential information between one signal and the neighbouring GND signal: the glitch appears in both. We can measure the difference among both victims. DM, Tardor

30 Power distribution Interlazed distribution minimizes the number of metal levels required. The thickness of each channel will vary according to the power consumption. DM, Tardor

31 Physical Design Cycle Compaction Compress the layout from all directions to minimize the chip area. Verification Check correctness of the layout. Include DRC (Design Rule Checking), circuit extraction (generate a circuit from the layout to compare with the original netlist), performance verification (extract geometric information to compute resistance, capacitance, delay,...) DM, Tardor

32 Conclusions The area of the blocks is predictable: Depends of the number of transistors and the spacing. It does not depend on the connections. The area of the connections is not much predictable. If the blocks are larger than the routing: the connections are determined by the separation among the blocks. If the routing dominates the blocks (in the same way as buses): The buses behave now like blocks. In any other case it is needed to simulate the connections to estimate their area (very sensible to the floorplanning). DM, Tardor

33 VLSI Design Cycle System Specification Circuit Design Architectural Design Physical Design Functional Design Fabrication Logic Design Packaging DM, Tardor

34 Circuit Design Outline What is Circuit Design Design Methods Design Styles Analysis and Verification Goal Understand circuit design topics DM, Tardor

35 What is circuit Design? Mapping logic to physical implementation implementation components component locations component wiring geometrical shapes examples TTL chips on a PC board single FPGA custom CMOS chip Issues level of circuit abstraction target implementation technology ai2.1 ai2.2 DM, Tardor

36 Implementation Methods Implementation methods integrated circuits programmable arrays - e.g. ROM, FPGA full custom fabrication hybrid integrated circuits thin film - built-in resistors thick film - ceramics silicon-on-silicon - multi-chip modules circuit boards discrete wiring - wire-wrap printed circuits Design rules topology and geometry constraints imposed by physics and manufacturing example: wires must be > 2 microns wide DM, Tardor

37 Design Methods Full custom design no constraints - output is geometry highest-volume, highest performance designs requires some handcrafted design 5-10 transistors/day for custom layout use to design cells for other methods primary CAD tools layout editor, plotter Cell-based design compose design using a library of cells at board-level, cells are chips cell = single gate up to microprocessor primary CAD tools partitioning placement and routing DM, Tardor

38 Design Methods Symbolic design reduce problem to topology let tools determine geometry (following design rules) can reuse same topology when design rules change e.g. shrink wires from 2 microns to 1 micron used mostly to design cells Procedural design cells are programs module generation - ROMs, RAMs, PLAs silicon compilation - module assembly from HLL Analysis and verification design rule checking - geometry widths, spacings ok? circuit extraction - geometry => circuit interconnect verification - circuit A == circuit B? DM, Tardor

39 Design Styles Gate array design FPGAs are a form of gate array Standard cell design General cell design Full custom design still used for analog circuits Implementation Methods Programmable Arrays Custom Design Styles Gate Array Standard Cell General Cell Custom Cell Symbolic Procedural Design Methods DM, Tardor

40 Gate Array Design Array of prefabricated gates/transistors Map cell-based design onto gates Wire up gates in routing channels between gates over top of gates (sea of gates) predefined wiring patterns to convert transistors to gates CAD problems placement of gates/transistors onto fixed sites global and local wire routing in fixed space DM, Tardor

41 Standard Cell Design Design circuit using standard cells cells are small numbers of gates, latches, etc. Technology mapping selects cells Place and wire them cells placed in rows all cells same height, different widths wiring between rows - channels CAD problems cell placement - row and location within row wiring in channels minimize area, delay DM, Tardor

42 General Cell Design Generalization of standard cells Cells can be large, irregularly shaped standard cells, RAMs, ROMs, datapaths, etc. Used in large designs e.g. Pentium has datapaths, RAM, ROM, standard cells, etc. CAD problems placement and routing of arbitrary shapes is difficult Datapath Cache RAM Decode PLA DM, Tardor Std. Cells ucode ROM

43 Case study Standard Cell implementation DM, Tardor

44 Standard Cell Implementation Cells designed in a certain pattern Due to the standard pattern they can be used in several circuits + Design reuse - Non-adaptative design DM, Tardor

45 A typical MOS gate VDD In1 In2 In3 PULL UP Out In1 In2 In3 PULL DOWN GND DM, Tardor

46 Standard Cell Structure DM, Tardor

47 Standard Cell Structure VDD P-diff Channel for interconnects (poly or metal) N-diff Poly Metal 1 Metal 2 Metal 3 GND Metal 4 Metal 5 DM, Tardor

48 VDD P-diff Standard Cell Structure The inputs of the transistors are connected to the poly layer. Horizontal connections are not recommendable since they increase the manufacturing costs. IN IN Poly IN IN Metal 1 N-diff Metal 2 GND IN Metal 3 Metal 4 Metal 5 DM, Tardor

49 Standard Cell Structure The inputs of the transistors are connected to poly or to metal in case they are lateral inputs. IN IN VDD P-diff Poly IN IN Metal 1 N-diff Metal 2 GND IN Metal 3 Metal 4 Metal 5 DM, Tardor

50 Standard Cell Structure Transistors are placed in a serial way. If we want them in paral lel we will have to add metal connections. VDD P-diff IN A OUT N-diff GND A B C DM, Tardor

51 VDD P-diff Standard Cell Structure Transistors are placed in a serial way. If we want them in paral lel we will have to add metal connections. IN A OUT N-diff OUT = A + B + C GND A B C DM, Tardor

52 Bit slice design We can design a block that implements all the operations for one bit (e.g. in a multi-bit design, as in an adder) We have to take into account all input, ouput and internal connections. Putting each cell together generates a regular and dense structure. Usual way of designing a processor s datapath (registers + FU + shifters). DM, Tardor

53 Bit slice design Block design from standard 1-bit cells DM, Tardor

54 High performance devices Mixture of full custom, standard cells and macro s Full custom for special blocks: Adder (data path), etc. Macro s for standard blocks: RAM, ROM, etc. Standard cells for non critical digital blocks Pentium DM, Tardor 2005 Power PC 54