Larger-than-Vdd Forward Body Bias in Sub-0.5V Nanoscale CMOS

Transcription

1 .2 Larger-than-Vdd Forward Body Bias in Sub-.V Nanoscale CMOS Hari Ananthan, Chris H. Kim and Kaushik Roy Dept. of Electrical and Computer Engineering, Purdue University 28 Electrical Engineering Building, West Lafayette IN , USA ABSTRACT This paper examines the effectiveness of larger-than-v dd forward body bias (FBB) in nanoscale bulk CMOS circuits where V dd is expected to scale below.v. Equal-to and larger-than V dd FBB schemes offer unique advantages over conventional FBB such as simple design overhead and reverse body bias capability respectively. Compared to zero body bias, they improve process-variation immunity and achieve 7% and 78% standby leakage savings at iso performance and iso active power at room temperature. We also suggest a novel temperature-adaptive body bias scheme to control active leakage and achieve 22% and 4% active power savings at higher temperatures. crease V t (and improve performance) have been proposed, both for logic and SRAM circuits [3, 4, 6]. Researchers have also pointed out the utility of FBB for process-variation immunity [, 7] and for designing ultimately-scaled lowtemperature CMOS circuits at nm gate length and.nm oxide thickness []. Categories and Subject Descriptors B.7. [Integrated Circuits]: Types and Design Styles; B.6. [Logic Design]: Design Styles General Terms Design, Performance Keywords Forward Body Bias, Process Variations, Sub-threshold Leakage, Junction Leakage. INTRODUCTION Dynamic threshold voltage (V t) the ability to dynamically tune MOSFET V t for high on-current during activemode (low-v t) and low off-current during standby-mode (high V t) helps the designer to more easily achieve system performance and power constraints. Dynamic body bias where the MOSFET body-source junction is forward biased in activemode and reverse biased in standby-mode is a popular technique to achieve dynamic-v t in bulk CMOS. Several circuit techniques that apply forward body bias (FBB) to de- Voltage (V) V dd V ss > V dd V fbb = V dd < V dd V dd (pmos) (nmos) V ss.2 Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ISLPED 4, August 9, 24, Newport Beach, California, USA. Copyright 24 ACM /4/8...$ Technology node (nm) Figure : FBB scaling trend. 8

2 Scheme DBB Device nmos pmos nmos pmos Gate Length 38 nm Oxide thickness.3 nm FBB V dd (V)..3 V t (mv) 2 2 Active body bias (V) Standby body bias (V) ZBB V dd (V)..4 V t (mv) Figure 2: BPTM 7nm device and circuit parameters used. V t = V th in the model file. The last 2 rows represent the parameters for the iso performance ZBB scheme with which the corresponding FBB scheme is compared. With technology scaling, supply voltage (V dd ) is approaching the sub-v regime. The ITRS roadmap [2] predicts V dd.v for Low Operating Power (LOP) systems at the 22nm node (year 26). Assuming a constant FBB voltage ( ) of approximately.v with scaling, it is conceivable that at V dd.v, becomes equal to and eventually greater than V dd. An interesting aspect of = V dd is the ability to use simple inverters to generate and distribute the body bias signals. With >V dd, interchanging the FBB signals while in standby-mode achieves reverse body bias for extra leakage reduction. This paper evaluates these two scenarios and identifies their benefits and shortcomings. We make four main contributions in this work. First, we examine the FBB scaling trend and confirm the optimality of larger-than-v dd FBB at sub-.v V dd for performance improvement. Second, we propose two novel schemes Digital and Over-Driven Body Bias that have unique advantages over conventional FBB schemes in terms of simple design overhead and reverse body bias capability. Third, we identify a new component of active leakage between the n-well and the p-well that limits the usefulness of larger-than- V dd FBB at high temperatures. Fourth, we suggest a novel Temperature-Adaptive Body Bias () scheme to overcome the active leakage problem. 2. FORWARD BODY BIAS IN SUB-.V VDD 2. Scaling trend The ITRS roadmap predicts that V dd for LOP systems is likely to scale from.8v at the 6nm node to.v at the 22nm node. Fig. shows the FBB scaling trend as V dd scales from.2v to.3v, from the 3nm node to beyond the 8nm node at the end of the roadmap. is limited by the turn-on voltage of the source/drain-to-body junction around.6v. A constant =.V is assumed to be applied symmetrically to both NMOS and PMOS devices as technology scales. As V dd scales to sub-.v, first becomes equal to and then greater than V dd. While Fig. suggests that V dd <.V occurs only at the end of the roadmap, sub-.v voltages are also likely to be used between the 6nm and 22nm nodes for two reasons. Firstly, the use of active-mode FBB allows further scaling of V dd while maintaining performance this suggests that the ac- Figure 3: Effect of junction leakage on performance with increasing FBB. Ring oscillator frequency (normalized) V.7V.2 Temp=27 o C Temp= o C FBB (V) CMOS Output levels (V) V FBB (V) Figure 4: Performance vs FBB. V dd =.V. tual V dd under FBB at a particular node may be smaller than the ITRS-projected value. Secondly, ultra-low power applications might scale V dd more aggressively than ITRS projections. 2.2 Optimal FBB for performance This subsection demonstrates the optimality of largerthan-v dd FBB for performance improvement in a 7nm technology, and argues why it is likely to remain optimal at smaller technologies. A BPTM 7nm MOSFET model provided by the Device Group at UC Berkeley [] with parameters shown in Fig. 2 is used to run HSPICE [3] simulations. A -stage ring oscillator with both NMOS and PMOS devices connected in a two-high stack is simulated for delay measurements. FBB decreases V t, increases on-current and thus improves performance. However, researchers have previously reported that the performance peaks at.4v and then starts decreasing in a 3nm technology [7]. Fig. 3 shows the operating currents in a V dd =.V two-input NAND structure with >.V. As FBB increases, the exponentially increasing forward biased source/drain junction leakage (I junc) fights the close-to-linearly increasing on-current 9

3 leakage power (normalized) ZBB,.V DBB,.V ZBB.4V.3V Gate length (nm) Delay (normalized) ZBB,.V DBB,.V ZBB.4V.3V Gate length (nm) Figure 6: Variation of active-mode (a) sub-threshold leakage, and (b) delay with gate length. Figure : Unique advantages of (a) DBB, and (b). (I on) and slows the charging/discharging of output and internal nodes. This contention between I on and I junc also starts degrading the output high and low voltage levels. The increase in junction parasitic capacitance with FBB slows down the circuit further. The value of at which performance peaks depends to a first order on the ratio I on/i junc smaller the ratio, smaller the maximum that the device can tolerate before the increase in I junc starts dominating the increase in I on. Thus, it is important to verify whether a sub-.v system has its performance peak in the V dd regime. Fig. 4 shows the dependence of performance on FBB for V dd =.V. The optimal is close to.7v at 27 o C, and to.6v at o C in terms of frequency. In the latter case, the voltage levels start degrading at approximately =.V worsening static leakage, noise margin and gate overdrive. A similar behavior is observed for V dd =.3V. This difference between room temperature and high temperature behavior has been observed before [7]; the reason is the exponential increase in I junc with temperature. These results show that V dd is optimal for performance improvement at the 7nm node, irrespective of temperature. There are two reasons why the optimal FBB is likely to remain at around.-.6v for smaller technologies. Firstly, smaller channel length devices with similar V dd s (.V and.3v) generate larger I on simply as a result of larger drainto-source electric fields. Secondly, well/halo doping levels increase with scaling, thus increasing the source/drain-tobody built-in voltage and decreasing I junc relative to I on. Both factors contribute to increasing the ratio I on/i junc and thus maintain or increase the optimal FBB value. 3. UNIQUE ADVANTAGES OF DBB AND Conventional FBB schemes require the generation and distribution of separate body bias voltage levels using global and local analog bias generation circuitry [6]. The = V dd scheme reuses V dd and V ss rails for body biasing. As shown in Fig. (a), regular digital inverters can be used to generate and distribute the body bias signals. Hence this scheme is called Digital Body Bias (DBB). DBB has significantly less design overhead compared to conventional FBB. Further, inverters can be placed closer to the circuit block to buffer the body voltage; this makes DBB more robust to substrate noise than conventional FBB. As Fig. (b) shows, the > V dd scheme is called Over-Driven Body Bias () because the body bias voltage levels are driven beyond the supply rails. This scheme requires additional bias generation circuitry; however, the overhead can be justified by the additional unique capability of to achieve reverse body bias (RBB) in standbymode by interchanging the active-mode biases. Fig. (b) shows how the NMOS FBB signal in active-mode acts as the PMOS RBB signal in standby-mode and vice-versa. This enables extra standby leakage reduction compared to conventional FBB. 4. DBB AND PROCESS-VARIATIONS AND POWER The following subsections compare process-variation immunity and standby leakage between DBB and schemes and the respective iso performance ZBB schemes implemented using the devices and V dd s shown in Fig. 2. The forward body bias enables DBB and to operate using higher- V t devices at lower V dd compared to the respective ZBB schemes. Essentially, the ratio CV dd /I on is maintained constant this ensures iso performance. A 6-bit ripple carry adder layout from a.µ technology is extracted and scaled to 7nm by multiplying device dimensions and parasitic RC s by the technology scaling factor κ = 7 =.28. The adder operates at. GHz for DBB (V dd =.V), and. GHz for (V dd =.3V).The ZBB operating voltages in comparison are.v and.4v respectively.

4 Active mode energy/cycle (fj) Activity (27 o C) ZBB/DBB Activity (27 o C) ZBB/ Figure 7: Active power versus activity at 27 o Cfor (a) ZBB (.V) and DBB (.V), and (b) ZBB (.4V) and (.3V). 4. Process-variation immunity Channel length is usually considered the most critical dimension of the MOSFET for process-variations. This is primarily because of drain-induced barrier lowering (DIBL). When a short-channel device is off (V gate = ) and a large voltage is applied between drain and source (V ds = V dd ), the drain-side depletion region extends into the channel region and lowers the barrier for the injection of carriers from the source to the channel, effectively decreasing V t.asaresult, slightly longer devices tend to operate slower (higher-v t), while slightly shorter devices tend to leak more (lower-v t). Forward body bias (V bs >) decreases drain-to-body voltage (V db ); this decreases the drain-to-channel junction depletion width and hence reduces DIBL [9]. Further, using activemode FBB enables reduction of V dd compared to ZBB at iso performance; lower V dd further reduces DIBL. Smaller DIBL essentially decreases the sensitivity of V t to channel length. Fig. 6 shows that as FBB increases, the worst-case leakage and delay variation decreases. The nominal gate length is 38nm; worst-case leakage occurs at -% (28nm) and worstcase delay at +% (48nm). Clearly, the variation is smaller in DBB and compared to the respective ZBB cases. 4.2 Standby leakage Standby leakage power is dominated by sub-threshold sourceto-drain leakage. Other nanoscale leakage components such as gate oxide tunneling and junction band-to-band tunneling (from source/drain-to-body) are negligible at such low voltages. By interchanging the active-mode body bias signals while in standby-mode, the DBB circuit is ZBB, while the circuit is under RBB. Compared to ZBB, both DBB and use higher-v t devices at lower V dd.bothhigh-v t and low V dd (through smaller DIBL) reduce sub-threshold leakage. DBB and achieve 7% and 78% reduction respectively compared to the respective ZBB cases. 4.3 Room temperature active power Active power includes two components: swtiching power and active leakage n + p + -epi e8 cm -3 p-substrate e cm -3 n-well e7 cm -3 pmos p + p + n + n + p + Oxide Isolation Forward bias current _ + V well = - nmos p-well e7 cm -3 Figure 8: Twin-well on p + -epi layer structure assumed for well leakage estimation. MOSFETs shown are not included in the simulation structure. Voltage (V) Well leakage (log) (A/u 2 ) V well Technology node (nm) Temp=27 o C Temp= o C DBB Conventional FBB V > well (forward bias) V dd V ss V < well (reverse bias) Figure 9: Well leakage scaling trend. V well = is superimposed on the scaling scenario from Fig.. P sw = αc load Vddf, 2 P leak = V dd I off = V dd (I sub + I junc + I well ), P sw is directly proportional to the activity factor α the fraction of cycles the adder is used for computation while in the active-mode. Active leakage in ZBB is predominantly sub-threshold leakage (I sub ). In DBB and, active leakage also includes forward-biased body-to-source junction leakage (I junc), and well leakage (I well ) between the n-well and the p-well (discussed in the next subsection). Both I junc and I well are negligible at room temperature. Fig. 7 plots active power against activity factor for ZBB/DBB and ZBB/ at 27 o C. A set of random transitions is applied to the adder and the average value is calculated. At 27 o C, DBB and consume approximately equal power

5 Active mode energy/cycle (fj) 3 2 Junction Well 2 activity =. activity =. 8% 2% 89% 3 % 2% 8% 27 7 Temperature (C) ZBB/DBB 27 7 Temperature (C) ZBB/ Figure : Active power versus temperature at. activity for (a) ZBB (.V) and DBB (.V), and (b) ZBB (.4V) and (.3V). compared to the respective ZBB cases at low activity DBB consumes 9% less, while consumes % more at α =.. The FBB schemes achieve significant savings at higher activities. This is because as α increases, switching power becomes a more significant component of active power than leakage; thus the effect of lower V dd becomes increasingly prominent. 4.4 Impact of active leakage at high temperature Assuming the circuit is clocked at the same frequency at all temperatures, switching power remains nearly constant as temperature increases. However, both sub-threshold and forward-biased junction leakage increase exponentially with temperature. A new component of leakage well leakage between the n-well and the p-well also becomes a significant fraction of active leakage. Fig. 8 shows the twin-well structure [8] assumed for well leakage simulations using a device simulator [4]. NMOS and PMOS devices are built in the p-well and the n-well respectively, and isolation between the wells is achieved through an oxide trench between and a p + -layer below. In ZBB, MOSFET body is tied to source NMOS body voltage is ( = V ss) and PMOS body voltage is V dd ( = V dd ). This ensures that V well ( ) is negative; thus the n- well to p-well junction is reverse-biased and well leakage is negligible. Fig. 9 shows the scaling scenario for FBB (derived from Fig. ) where as V dd scales under constant.v FBB, becomes smaller than at around 9nm that is, V well >. This results in a forward bias across the wells, and well leakage increases exponentially with V well and with temperature. Fig. plots active power against operating temperature for ZBB/DBB and ZBB/ at the worst-case activity α =.. The percentages shown depict the penalty associated with the FBB schemes over the respective ZBB schemes. While DBB and consume near-iso active power at lower temperatures, the increase in active leakage starts overwhelming the decrease in switching power at higher temperatures. Thus, DBB and are attractive FBB schemes for Figure : scheme. near-room temperature operation. The advantages include simple design overhead (DBB), reverse bias capability (), improved process-variation immunity, lower standby leakage and equal or lower active power at iso performance compared to ZBB. However, the increase in active leakage increases the active power penalty and limits their usefulness at higher temperatures.. TEMPERATURE-ADAPTIVE BODY BIAS Researchers have shown that at low operating voltages (sub-v), drain current increases with temperature as opposed to the usual trend at higher V dd s []. I on is directly proportional to the product µ(v dd V t) α,whereµ is the carrier mobility and α is a technology-dependent parameter. As temperature increases, both µ and V t decrease, however the former effect is usually more dominant [6]. Thus I on (and hence performance) decreases as temperature increases in high-v dd systems. This trend is reversed at low-v dd decrease in V t has a bigger impact on I on than mobility degradation. Thus, the circuit performs faster at higher temperatures than the clock frequency. This fact has been exploited to throttle performance and save switching power by lowering V dd at high temperature [], and to suppress the impact of temperature variations on performance in sub-threshold logic circuits through adaptive body biasing [2]. We exploit this positive temperature dependence to suggest a Temperature-Adaptive Body Bias () scheme that overcomes the high temperature active leakage problem in DBB and. Previously proposed feedback-based body bias generation schemes that track critical path delay [] as shown in Fig. can be used to implement a temperature-adaptive system that scales down as temperature increases, while maintaining performance. Fig. 2(a) shows the increase in performance with temperature for ZBB, DBB and, and the constancy of performance for ; Fig. 2(b) plots the corresponding FBB voltage applied. While DBB and apply constant large biases, scales down by around.3-.4v at o C to maintain performance while reducing active leakage. This reduction is shown in Fig. 3 reduces active power compared to ZBB even at high temperature/low activity. The reduction is 22% for the DBB case and 4% for the case at α =.. The savings remain nearly constant at higher activities. 2

6 Ring oscillator frequency (normalized) V =.V/.V dd V =.3V/.4V dd ZBB DBB ZBB Temperature ( o C) FBB applied (V) ZBB DBB Temperature ( o C) Figure 2: Comparison between ZBB/DBB, ZBB/ and (a) Performance vs Temperature, and (b) FBB applied. Active mode energy/cycle (fj) Junction Well Activity ( o C) ZBB/DBB/ Activity ( o C) ZBB// Figure 3: Active power comparison at o Cbetween (a) ZBB (.V), DBB (.V) and (.V), and (b) ZBB (.4V), (.3V) and (.3V). Thus, for high temperature operation, is an attractive FBB scheme with V dd at near-room temperatures and progressively decreasing at higher temperatures. The design overhead for is greater than DBB and. However it is justified by the advantages compared to ZBB better process-variation immunity, lower standby leakage and lower active power at iso performance at all temperatures. 6. CONCLUSION Given that V dd is scaled aggressively with technology for low power systems, forward body bias in nanoscale sub-.v V dd systems is evaluated and larger-than-v dd FBB is found to be an optimal design strategy for performance improvement. We propose two novel FBB schemes Digital and Over-Driven Body Bias that provide unique advantages over conventional FBB in terms of simple design overhead and reverse body bias capability respectively. DBB and can be used to increase device-v t and decrease V dd, and thus save standby leakage compared to ZBB at iso performance. They also reduce the spread in delay and leakage due to process-variations. While these schemes consume equal or less active power than ZBB for near-room temperature operation, excessive active leakage including well leakage limits their usefulness at higher temperatures. A novel Temperature-Adaptive Body Bias scheme is proposed to control active leakage by scaling down as temperature increases, thus saving active power while maintaining performance. 7. ACKNOWLEDGEMENT This work was supported in part by Semiconductor Research Corporation, and by IBM and Intel. 8. REFERENCES [] Berkeley Predictive Technology Model, 22, ptm. [2] International Technology Roadmap for Semiconductors, 23, [3] K. Ishibashi, T. Yamashita, Y. Arima, I. Minematsu, and T. Fujimoto. A 9µW MHz 32b adder using self-adjusted forward body bias in SoCs. In Intl. Solid-State Circuits Conf. Dig. Tech. Papers, pages, 23. [4] C. Kim, J.-J. Kim, S. Mukhopadhyay, and K. Roy. A forward body-biased low-leakage SRAM Cache: device and architecture considerations. In Proc. Intl. Symp. Low Power Electronics and Design, pages 6 9, 22. [] M. Miyazaki, G. Ono, and K. Ishibashi. A.2-GIPS/W Microprocessor using speed-adaptive threshold-voltage CMOS with forward bias. IEEE J. Solid-State Circuits, 37(2):2 27, February 22. [6] S. Narendra et al. A.V GHz communications router with on-chip body bias in nm CMOS. In Intl. Solid-State Circuits Conf. Dig. Tech. Papers, pages , 22. [7] S. Narendra, A. Keshavarzi, B. Bloechel, S. Borkar, and V. De. Forward body bias for microprocessors in 3nm technology generation and beyond. IEEE J. Solid-State Circuits, 38():696 7, May 23. [8] S.Odanaka,T.Y.amdN.Shimizu,H.Umimoto,and T. Ohzone. A self-aligned retrograde twin-well structure with buried p + -layer. IEEE Trans. Electron Devices, 37(7):73 742, July 99. [9] Y. Oowaki et al. A sub-.µm circuit design with substrate-over-biasing. In Intl. Solid-State Circuits Conf. Dig. Tech. Papers, pages 88 89,42, 998. [] C. Park et al. Reversal of temperature dependence of integrated circuits operating at very low voltages. In Proc. Intl. Electron Devices Meeting, pages 7 74, 99. [] K. Shakeri and J. Meindl. Temperature variable supply voltage for power reduction. In Proc. IEEE Computer Society Annual Symp. VLSI, pages 64 67, 22. [2] H. Soeleman, K. Roy, and B. Paul. Robust sub-threshold logic for ultra-low power operation. IEEE Trans. VLSI, 9():9 99, Feb 2. [3] Synopsys. HSPICE Ver [4] Synopsys. Taurus-Device Ver [] Y. Taur. CMOS scaling beyond.µm: how far can it go? In Proc. Intl. Symp. VLSI Tech., Systems and Appl., pages 6 9, 999. [6] Y. Taur and T. Ning. Fundamentals of modern VLSI devices. Cambridge University Press, 23. 3