Control Synthesis and Delay Sensor Deployment for Efficient ASV designs

Transcription

1 Control Synthesis and Delay Sensor Deployment for Efficient ASV designs C H A O FA N L I < C H AO TA M U. E D U >, T E X A S A & M U N I V E RS I T Y S A C H I N S. S A PAT N E K A R, U N I V E RS I T Y O F M I N N ESOTA J I A N G H U, T E X A S A & M U N I V E RS I T Y This work is partially supported by NSF and Semiconductor Research Corporation (SRC) 1

2 Motivation Resilience against Circuit Variation Delay Sensor Process variation Timing variation Worse propagation delay Transistor aging Warning signal Increase timing margin 2

3 Introduction Adaptive Design for Variation Tolerance Delay sensor designs Critical Path Replica Canary Flip-Flop Razor-like shadow flip-flop Resilience for variation Adaptive Supply Voltage (ASV) Adaptive Body Bias (ABB) Forward Body Bias (FBB) Reverse Body Bias (RBB) 3

4 Introduction Adaptive Supply Voltage designs Coarse-grained ASV Less adaptive blocks and delay sensors One-to-one association of sensors and blocks Simple control Fine-grained ASV More adaptive blocks and delay sensors One sensor may reflect multiple blocks Complex control Core/ Block A Delay Sensor 1 Core/ Delay Block B Sensor 2 Coarse-grained ASV Adaptivity Block B Adaptivity Block A Combinational Logic Circuit Fine-grained ASV Delay Sensor 1 Delay Sensor 2 Delay Sensor 3 4

5 Introduction Voltage Interpolation[1] VddH 1.2V VddL 1.0V Effective Vdd 1.13V Block 1 Block 2 Block 3 Combinational circuits Voltage Interpolation is one of the fine-grained ASV designs Only two voltage regulators [1] Liang. X. etc. Revival: A variation-tolerant architecture using voltage interpolation and variable latency

6 Overview of Design Flow Clustered placement Initial placement Timing analysis Clustering[1] Delay sensor deployment Control synthesis considering [2] Adaptivity assignment[2] Final placement [1] A. Lu, H. He and J. Hu, Proximity Optimization for Adaptive Circuit Design, ACM International Symposium on Physical Design, [2] H. He, J. Wang and J. Hu, Collaborative Gate Implementation Selection and Adaptivity Assignment for Robust Combinational Circuits, ISLPED,

7 Control Synthesis Adaptivity Block B Adaptivity Block A Adaptivity Block C Combinational Logic Circuit Canary FF 1 Canary FF 2 Canary FF 3 Tune some blocks to high VDD with min power overhead such that no warning signal at sensors 7

8 Control Synthesis Rule-Based method Turn one block to high VDD based on one sensor warning Adaptive blocks Delay sensors Capacity = 1 Cost = 0 S A B C Capacity = 1 Cost Capacity = 1 Cost = 0 Cost is inversely proportional to the overlap T Min-Cost maxflow One-to-one association 8

9 Control Synthesis Finite-State Machine (FSM): Overview Phase I: Initial response Ensure all timing warnings responded with minimum power overhead Phase II: Incremental response Ensure all timing warnings removed Initial adaptivity block states Phase I Flag matrix Dominance graph Pruned graph Control logic Updated adaptivity block states Delay Sensor states Phase II Flag matrix Control logic Updated adaptivity block states 9

10 Control Synthesis FSM: Inputs, states and flag matrix Input vector State (output) vector Flag matrix The states of delay sensors The voltage levels of adaptivity blocks Relationship between sensors and adaptive blocks Adaptivity Block B Adaptivity Block A Adaptivity Block C Combinational Logic Circuit Canary FF 1 Canary FF 2 Canary FF 3 State vector b i = {0, 1} b A b B b C Input vector s j = {0, 1} s 1 s 2 s Flag matrix 10

11 Control Synthesis Finite-State Machine: Phase I Example flag matrix Adaptivity blocks Sensors Definitions: Maximum Single-Response Scenario {s1,s2,s3}, {s4,s5,s6} Single-Response Scenario of {s1,s2,s3} {s1,s2,s3} {s1,s2}, {s1,s3}, {s1,s2} {s1}, {s2}, {s3} Compensated by adaptivity block #2 Adaptivity block #4 has large overlap with the fan-in cone of sensor 3 11

12 Graph Pruning Finite-State Machine: Phase I b2 {1,2,3} b1 {4,5,6} b2 {1,2,3} b1 {4,5,6} b2 b2 b4 {1,2} {1,3} {2,3} b1 b1 b5 {4,5} {4,6} {5,6} b2 b4 {1,2} {2,3} b1 b1 b5 {4,5} {4,6} {5,6} b6 b4 b3 {1} {2} {3} b1 b5 b5 {4} {5} {6} b6 b4 b3 {1} {2} {3} b1 b5 b5 {4} {5} {6} Before Pruning After Pruning Redundant Sensor Scenario : Overhead larger than that successor scenario Overhead of b6 and b3 less than b2 {1,3} pruned 12

13 Initial Response Finite-State Machine: Phase I b2 b2 {1,2,3} b4 {1,2} {2,3} b6 b4 b3 {1} {2} {3} Scenario sets b1 {4,5,6} b1 b1 b5 {4,5} {4,6} {5,6} b1 b5 b5 {4} {5} {6} b 5 = (s 6 + s 5 ) (s 4 ) b 4 = s 2 s 1 Min scenario is a minterm 1, 2 s 1 s 2 { 5, 6 } s 6 + s 5 B 5 = s 6, s 5, s 6, s 5 B max 5 = {s 6, s 5 } B min 5 = s 6, {s 5 } B 4 = s 2, s 3, s 2 B max 4 = {s 3, s 2 } B min 4 = s 2 Complement of max scenario is a minterm 4, 5, 6 5, 6 s 4 1, 2, 3 {2, 3} s 1 13

14 Incremental Response Finite-State Machine: Phase II Initial State Partial Finite-State Machine: Numbers in the circle denote tuning knob states Number by the edge denote sensor states Initial Response Incremental Response: Greedy changes until no warnings 14

15 Delay Sensor Deployment Goals of delay sensors Monitor all paths whose delay variations pose a risk on timing violation a b c Canary FF 1 FF2 Canary FF 3 Large overlap among timing paths to different flip-flops Need tradeoff between coverage and criticality 15

16 Delay Sensor Deployment Formulation 1: maximize coverage with number of delay sensors no more than a upper bound Iteratively select FF with maximum priority value p i = d i w d i di 16

17 Delay Sensor Deployment Example of Formulation 1 d i di p i = d i w d i is the total path delay, d i is the uncovered path delay p i d = (2.9, 3, 3.1) d = (1.8, 1.5, 1.2) w 17

18 Delay Sensor Deployment Formulation 2: minimize number of delay sensors with coverage no less than a lower bound (Set Cover Problem) d Covered if p i = i di < p th Find minimum number of flips-flops that make almost all critical paths covered Solved iteratively by choosing FF with maximum p 18

19 Experiment Encounter Final placement DEF file Routing Parasitic extraction Nangate FreePDK library SPEF file Timing yield / Power Consumption Monte Carlo simulations Timing paths Static Timing Analysis PrimeTime 19

20 Results Timing Yield 1 Coarse Rule FSM All Low edit_dist matrix_mult vga_lcd b19 leon3mp leon2 netcard Average 20

21 Results Leakage Power Coarse Rule FSM All Low edit_dist matrix_mult vga_lcd b19 leon3mp leon2 netcard Average 21

22 Number of covered critical paths Results Delay Sensor Deployment Result for b Previous work Formulation 1 Formulation Number of sensors 22

23 Conclusion Proposed two control synthesis methods for efficient ASV designs Rule-based method Finite-state machine method Proposed delay sensor deployment method that achieves better balance between Coverage of timing paths Criticality of timing paths Our methods achieves approximately 20% leakage power reduction compared to coarse-grained designs 23

24 Thanks Q & A 24