induced Aging g Co-optimization for Digital ICs

Transcription

1 International Workshop on Emerging g Circuits and Systems (2009) Leakage power and NBTI- induced Aging g Co-optimization for Digital ICs Yu Wang Assistant Prof. E.E. Dept, Tsinghua University, China

2 On-going Work in NICS CAD Group Reliability/power aware design methodology NBTI+Leakage [ISQED/DATE/ISLPED 2009] Soft error [ISQED 2008] Power gating aware MPSoC scheduling [ISVLSI 2009] [submitted to CASES 2009] Parallel Circuit Partitioning and Simulation DCCB based circuit partitioning [submitted to ASICON2009] GPU/FPGA based machine learning acceleration [FPL 2009] [submitted to ICPADS 2009]

3 Background: Leakage The circuit total power(p total)can be calculated as: Ptotal = Pswitch + Pshortcircuit + Pleakage dynamic power { g static power As technology scales, the dynamic power of one transistor decreases, while leakage power increases. Leakage is more than 50% of the total power. The modeling and optimization has been studied for 10 years or more.

4 Leakage reduction techniques Standby time techniques Power Gating Input Vector Control Body biasing adapt Vth during the standby time Adapt Vdd during the standby time Run time techniques DVTS dynamic Vth scaling DVS dynamic Vdd scaling Design time techniques Dual Vth Dual Vdd Gate sizing

5 Aging due to NBTI Negative Bias Temperature Instability Conditions PMOS transistor NBTI Negatively biased elevated temperature Impact of NBTI on circuit performance a shift in threshold voltage a significant increase in the delay of PMOS devices, and result in about 10-20% degradation in circuit speed

6 NBTI mitigation techniques Lower temperature, Vdd, and signal probability [DAC06] NBTI-aware Sizing [DATE06] NBTI-aware Synthesis [DAC07] Guard banding [ASPDAC08] Dynamic Adjustment (Vdd, Vth) [ASPDAC09] Input Vector control [DATE 07, MICRO 07] Memory NBTI mitigation [ISQED06]

7 Power and Robustness Trade-off Low power antagonistic to robust design Increased sensitivity to Vt variation in low voltage operation Clock gating and low power modes increase power grid noise Power optimization equalizes path delays Conversely: Design margins increase circuit robustness at tthe expense of power # of paths # of paths Critical path delay delay POWER OPTIMIZATION delay

8 Leakage and NBTI co-optimization Simulation platform Static and Statistical Optimization method Input vector control [DATE 2007, ISQED 2009] Internal node control [DATE 2009] Supply Voltage Assignment [ISLPED 2009]

9 Leakage and NBTI co-optimization Simulation platform Static and Statistical Optimization method Input vector control [DATE 2007, ISQED 2009] Internal node control [DATE 2009] Supply Voltage Assignment [ISLPED 2009]

10 Simulation Platform Active time Statistical Signal Probability (SP) of inputs Standby time Input Vector Generator Timing i Libs Commercial Static Timing Analysis tool Logic Simulator Run time internal node SP Standby time internal node state Potential Critical Paths (PCP) Transistor level NBTI modeling Path-based NBTI-aware Timing Analysis Lookup table based leakage calculation NBTI-induced circuit degradation and leakage power

11 Do once for the whole simlulation Active time Statistical Signal Probability (SP) of inputs Standby time Input Vector Generator Timing Libs Commercial Static Timing Analysis tool Logic Simulator Run time internal node SP Standby time internal node state Potential Critical Paths (PCP) Transistor level NBTI modeling Path-based NBTI-aware Timing Analysis Lookup table based leakage calculation NBTI-induced circuit degradation and leakage power

12 Active time Statistical Signal Probability bbili (SP) of inputs Standby time Input Vector Generator Timing Libs Commercial Static ti Timing i Analysis tool Logic Simulator Run time internal node SP Standby time internal node state Potential Critical Paths (PCP) Transistor level NBTI modeling Path-based NBTI-aware Timing Analysis Lookup table based leakage calculation NBTI-induced circuit degradation and leakage power

13 IVC for both Leakage and NBTI Both depend on the input vectors For NBTI 1 is the best input for NBTI 0i is the worst For Leakage, it is not the same story the best case input patterns to mitigate the leakage for NAND/AND/INV gates are all 0 s at the inputs for NOR/OR/BUF gates are all 1 s 1s at the inputs. That is why we may get a trade off between leakage and NBTI Input Vector control can compensate 30% delay degradation induced by NBTI, and mitigate t 10% total t leakage. But the efficacy is limited it because input vectors can only control limited stages of internal circuits. The theoretic potential of node control for NBTI compensation could be up to 70%.

14 Leakage and NBTI Distributions NBTI and leakage distributions for different circuits

15 Input dependency of NBTI and leakage Low leakage Low leakage and degradation Low degradation

16 Why Internal Node Control? We need to find the optimal input vectors for low leakage and degradation IVC? Finding the optimal Input Vector is time consuming The effect of IVC will be diminished when the circuit becomes larger INC can control more internal gates in the circuit

17 Internal Node Control for Leakage Gate Replacement DAC 2005,2006 Control Point Insertion TCASII Sleep transistor insertion DATE 2007 G G

18 Why we choose gate replacement Gate Replacement Topology not changed Gate structure not changed Standard library can be directly used G G Changed gate structure Changed circuit topology

19 Internal node control For leakage G G For NBTI DGR [TVLSI06] and DCBGR[DAC06] algorithm for cooptimization. DGR: Direct Gate Replacement. First NBTI in Critical path, and then leakage in the non-critical path DCBGR: Divide the circuit into trees, and then perform the NBTI and leakage optimization.

20 An example for C17

21 Implementations C++ for most of the codes with PrimeTime 65nm library Some key technology parameters are: Vdd = 1.0V ; Vth = 0.20V; Tox= 1.2nm ISCAS85 benchmark and some ALU circuits are used to evaluate our algorithms. Tactive and Tstandby are both set to be 378K Ratio of active and standby time is set to be 1:9. Input probabilities of all the input nodes at active time to 0.5 for simplicity. The circuit lifetime is set to be 10 years. 5% performance relaxation ation at time 0 is allowed

22 INC results (1) Results of 10K random IV search in DGR

23 INC results (2):DGR for leakage or NBTI only INC is more effective than IVC Larger circuits lead to better results Area increase is different for leakage and NBTI Compare to the best result of IVC

24 INC results (3):DGR for leakage and NBTI Compare with the results of IVC for simultaneously NBTI and leakage reduction INC is more effective than IVC Larger circuits lead to better results

25 INC results (4): DCBGR for leakage and NBTI simultaneous

26 INC is more effective than IVC. INC results For larger circuits, it INC get better results than average. DCBGR algorithm is better than DGR algorithms, faster and better. d0 is the original circuit delay at time 0 d01 is the original circuit delay at10years d1 is the delay after gate replacement at time 0 d11 is the circuit degradation after gate replacement at 10years Our percentage %=[ 1 - (d11-d0 ) / (d01-d0 ) ] *100%

27 Leakage and NBTI co-optimization Simulation platform Static and Statistical Optimization method Input vector control [DATE 2007, ISQED 2009] Internal node control [DATE 2009] Supply Voltage Assignment [ISLPED 2009]

28 Statistical platform Leakage lookup table Input vector Circuit net list Logic simulator Transistor level NBTI modeling Timing libs Statistical i leakage Statistical i timing i power calculation analysis The result of statistical leakage and NBTI-aware circuit delay

29 Statistical Model (1) Vth variation model, assume that Vth can be modeled as a Gaussian distribution. 1 2 μ V th th 1 σ th PDF( Vth) = e 2πσth Assume that the logically close gates are also spatially close, and the threshold voltage of gate v i is correlated with some nearest gates, each correlation coefficient is: ρ ( v, v ) = ρ ( ρ > ρ i i± k k i j for any i < j ) 2

30 Statistical Model (2) The threshold voltage of each gate v i is expressed as linear combinations of its mean value and random variables: n = + Δ + Δ + Δ = = V V a V a V a V ith, i 0 i j i + j j i j j 1 j 1 Assume that a i s are Gaussian distribution, then ρ i s can be calculated as: ρ k = n k 0 k i i+ k i j i= 1 i+ j= k, i 1, j 1 n 2 2 a0 + 2 ai i= 1 2aa + 2 aa + aa n

31 Supply Voltage Assignment Technique Dual Vdd Assignment + Dynamic Vdd Scaling Why dual Vdd? High Vdd is used to compensate for NBTI-induced degradation on critical gates, while low Vdd is used to reduce leakage power on other gates. Why dynamic scaling? One-time solutions at design time will lead to large power and area overhead. Variations will affect the circuit performance. First Step: Dual Vdd Assignment Second Step: Dynamic Vdd Scaling

32 Supply Voltage Assignment Technique Second Step: Dynamic Vdd Scaling Delay specification Determine the optimal high Vdd, to ensure NBTI-induced degradation and leakage power are simultaneously minimized during the V ddhigh (t i ) V ddhigh (t i+1 ) following time interval. t t t F = A ( μ ) ( ) Dt ( 1) + 3σ ( 1) ( ) 3 i Dt + B μ i Lt + σ + + i Lt ( i) Determine the optimal low Vdd, to reduce leakage power as more as possible during the following time interval. D () v = D () v + C D () v relax current slack Predict the next time node at which the circuit delay will exceed the specification and the supply voltages need to be scaled again. [CICC 2008][ASPDAC2009] μ Td n () t = μ (0)(1 + Ct ) Td i-1 i i+1

33 Simulation Results Delay Distribution considering NBTI and Vth variation Proba ability Di istributio on Funct tion Delay(ns)

34 Simulation Results NBTI induced degradation comparison (C1908) 5.5 Nominal delay Our approach De elay mean n(ns) E E E E E E+10 Time(second)

35 Simulation Results Leakage power comparison (c1908) 7 Leakage e mean( (1E-4mW W) Nominal leakage Our approach 5 1.0E E E E E E Time(second)

36 Simulation Results The voltage scaling (c1908 vs c7552) ) Voltage(V) High Vdd Low Vdd E+00 1.E+02 1.E+04 1.E+06 1.E+08 1.E+10 Time(s) c1908 Voltage(V) High Vdd Low Vdd E E E E E E+10 Time(second) c7552

37 37 Simulation Results

38 Simulation Results Comparing with Single Vdd Assignment Delay(ns s) 5.2 Delay (Dual Vdd) 10 Delay (Single Vdd) Leakage (Dual Vdd) 8 5 Leakage (Single Vdd) E+00 1.E+02 1.E+04 1.E+06 1.E+08 1.E+10 Time(s) Le eakage power(1e E-4mW)

39 Simulation Results Compare scheduled technique [ASPDAC2009] with our SVA for c499 Delay mean(ns) Nominal design Scheduled voltage scaling Our approach 2 1.0E E E E E E+10 Time(s) 39

40 Conclusions We build a NBTI and leakage co-optimization platform. We try to investigate some gate level optimization techniques for NBTI and leakage co-optimization. Input vector control Internal node control Supply Voltage Assignment NBTI/leakage co-optimization in other design levels will be our future work.

41 Acknowledgement NSF of China MSRA AMD 863 project My collaborators from Tsinghua University, ASU, and PSU.

42 Thank you for your attention. Q & A