Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing *

Transcription

1 Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing * Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas University of Illinois at Urbana-Champaign * to appear in MICRO-40, December 2007

2 Motivation Technology scaling continues More and more transistors every generation! However... Chips are increasingly affected by parameter variation Intel Corp. 2

3 4+ Parameter Variation F G??F Process variation Manufacturing at low feature sizes Temperature variation "#.+ "B5 Uneven activity distribution "()*#:+C$ "#-#D9: Supply voltage variation IR drop, di/dt noise "#.+ "B5 "()*#:+C$ "#-#D9: Intel Corp. A? " 3

4 Effects of Parameter Variation Higher power consumption Lower frequency Uncertainty in the design process 4

5 Outline A Model of Process Variation Dynamic Fine-Grain Body Biasing Evaluation Conclusions 5

6 Outline A Model of Process Variation Dynamic Fine-Grain Body Biasing Evaluation Conclusions 6

7 A Model For Process Variation Fast, simple and parameterizable model We model two key process parameters: Transistor critical dimension (Leff) and threshold voltage (Vth) We also model temperature effects 7

8 Variation Components Granularity: Within die Die-to-die Within die Die-to-die WID variation: Systematic variation Random variation 8

9 A Model For Process Variation Variation in any parameter P: ΔP = ΔPD2D + ΔPWID = ΔPD2D + ΔPrand + ΔPsys We focus on WID variation D2D is a chip-wide offset to ΔPWID Random and systematic components Modeled as normal distributions Treated separately - impact different levels of the microarchitecture 9

10 Systematic Variation We divide the chip into a grid of points Each point has one random value of ΔPsys Multivariate normal distribution (μsys=0, σsys) Characterized by a correlation function: Px r corr(p x, P y ) = ρ(r) ; r = x y Py Correlation is position independent and isotropic For ρ(r) we choose the spherical model 10

11 Spherical Model ρ(r) 1 ρ(r) = 1 3r 2φ + r3 2φ 3 : (r φ) 0 : otherwise 0 0 φ r Stronger correlation Weaker correlation Px Py r Px r Py Matches measured data [Friedberg et al. 05] 11

12 Random Variation Random variation - transistor level We model it analytically as a normal distribution Both ΔPrand and ΔPsys are normal and independent with σrand and σsys σ total = σ 2 rand + σ2 sys 12

13 Outline A Model of Process Variation Dynamic Fine-Grain Body Biasing Evaluation Conclusions 13

14 Body Biasing Well known technique for Vth control A voltage is applied between source/drain and substrate of a transistor Forward body bias Reverse body bias FBB - Vth - Freq - Leak RBB - Vth - Freq - Leak Useful knob to control frequency and leakage 14

15 Body Bias Design Space Space Time Static BB fixed for chip lifetime Simple adaptation FBB in active mode RBB in standby Dynamic BB changes with T and workload Chip-wide D2D variation D2D variation, power, performance [Intel Xscale] [Intel s 80-core chip] Fine-grain WID variation WID variation, power, performance WID variation T variation (space and time) [Tschanz et al] 15

16 Body Bias Design Space Space Time Static BB fixed for chip lifetime Simple adaptation FBB in active mode RBB in standby Dynamic BB changes with T and workload Chip-wide D2D variation D2D variation, power, performance [Intel Xscale] [Intel s 80-core chip] Fine-grain S-FGBB WID variation WID variation, power, performance WID variation T variation (space and time) [Tschanz et al] 15

17 Body Bias Design Space Space Time Static BB fixed for chip lifetime Simple adaptation FBB in active mode RBB in standby Dynamic BB changes with T and workload Chip-wide D2D variation D2D variation, power, performance [Intel Xscale] [Intel s 80-core chip] Fine-grain S-FGBB WID variation WID variation, power, performance WID variation T D-FGBB variation (space and time) [Tschanz et al] 15

18 Motivation for D-FGBB Body bias trades off frequency for leakage Optimal body bias: The lowest FBB or highest RBB s.t. circuit delay meets frequency target Relative Switching Frequency Vth = 0.120V Vth = 0.135V Vth = 0.150V Vth = 0.165V Vth = 0.180V Circuit delay changes with temperature Therefore optimal BB changes with temperature Temperature (C) 16

19 Motivation for D-FGBB Body bias trades off frequency for leakage Optimal body bias: The lowest FBB or highest RBB s.t. circuit delay The meets goal of frequency D-FGBB is to keep the target body bias optimal as T changes Relative Switching Frequency Vth = 0.120V Vth = 0.135V Vth = 0.150V Vth = 0.165V Vth = 0.180V Circuit delay changes with temperature Therefore optimal BB changes with temperature Temperature (C) 16

20 Finding the Optimal BB Measure the delay of each BB cell Critical path replicas to sample cell delay Phase detector times the critical path replica If slow - FBB signal raised If fast - RBB signal raised CLK Critical Path Replica extra delay Phase Detector slow fast FBB RBB Sample Point 17

21 Applying Fine Grain BB RBB RBB FBB FBB Sample Points FBB FBB RBB RBB AND DEC Local Bias Generator N-CNT D2A NMOS V bb OR INC P-CNT D2A PMOS V bb RBB RBB FBB FBB FBB FBB RBB RBB Body Bias Cell 18

22 Applying Fine Grain BB RBB RBB FBB FBB Sample Points FBB FBB RBB RBB AND DEC Local Bias Generator N-CNT D2A NMOS V bb OR INC P-CNT D2A PMOS V bb RBB RBB FBB FBB FBB FBB RBB RBB Body Bias Cell 18

23 Applying Fine Grain BB RBB RBB FBB FBB Sample Points FBB FBB RBB RBB AND DEC Local Bias Generator N-CNT D2A NMOS V bb OR INC P-CNT D2A PMOS V bb RBB RBB FBB FBB FBB FBB RBB RBB Body Bias Cell 18

24 Applications of D-FGBB Operating environments Normal High Performance Low Power S-FGBB Improve chip operating point Improve chip operating point Save leakage power D-FGBB Save leakage power Increase average frequency Save leakage power 19

25 Applications of D-FGBB Operating environments Normal High Performance Low Power S-FGBB Improve chip operating point Improve chip operating point Save leakage power D-FGBB Save leakage power Increase average frequency Save leakage power 20

26 Improving a Chip s Operating Point Acceptable region NoBB High power frequency Leakage power limit 21 Low frequency leakage (a) Figure 10.

27 Improving a Chip s Operating Point Post-manufacturing calibration phase: 1. Bring chip to Tcal 2. Set target frequency Fcal 0, and run at full load 3. BB is adjusted automatically 4. Measure total power Pcal: if Pcal<Ptarget, Fcal 1 =Fcal 0 ++, else Fcal 1 =Fcal Repeat if needed, until Pcal Ptarget Fcal i becomes the chip s frequency 22

28 D-FGBB Adapts to Changes in T Calibration temperature Tcal is conservative Average T much lower: Tcal 100 Tmax Tavg Temperature (C) IntQ IntReg LdStQ IntExec IntMap DTB ITB FPQ FPReg FPMap Bpred FPAdd FPMul Dcache Icache L2Cache Functional Units 23

29 D-FGBB Saves Leakage Power S-FGBB finds and sets Fcal D-FGBB adjusts dynamically to T changes to save power while running at Fcal S-FGBB at Tavg Fcal S-FGBB at Tcal Frequency D-FGBB at Tavg Original chip Leakage limit at Tcal Leakage 24

30 Applications of D-FGBB Operating environments Normal High Performance Low Power S-FGBB Improve chip operating point Improve chip operating point Save leakage power D-FGBB Save leakage power Increase average frequency Save leakage power 25

31 D-FGBB Improves Performance Average power Pavg<Pmax D-FGBB is used to push the chip to Favg>Fcal, as long as P<Pmax S-FGBB at Tavg D-FGBB at Tavg Fcal S-FGBB at Tcal Frequency Original chip Leakage limit at Tcal Leakage 26

32 Applications of D-FGBB Operating environments Normal High Performance Low Power S-FGBB Improve chip operating point Improve chip operating point Save leakage power D-FGBB Save leakage power Increase average frequency Save leakage power 27

33 D-FGBB Saves Leakage Power The chip runs at its original Forig D-FGBB adjusts dynamically to T changes to save power while running at Forig Frequency D-FGBB at Tavg Forig Original chip Leakage limit at Tcal Leakage 28

34 Outline A Model of Process Variation Dynamic Fine-Grain Body Biasing Evaluation Conclusions 29

35 Evaluation Infrastructure Statistical package R to generate variation maps for 200 chips SESC - cycle accurate microarchitectural simulator - execution time, dynamic power Mix of SPECint and SPECfp benchmarks HotLeakage, SPICE model - leakage power Hotspot - temperature estimation 30

36 Evaluation Infrastructure HotLeakage BSIM3 SPICE T leakage power F R statistical package Variation model, BB leakage power under variation SESC Simulator dynamic power Hotspot CMP Floorplan Frequency, power of each chip, under variation 31

37 Evaluation Methodology 4-core CMP, based on Alpha nm technology, 4GHz Vth variation: σvth/μvth= , σsys=σrand Leff variation σleff= σvth/2 Vdd=1V, Vth0=150mV, Vbb= ±500mV 32

38 CMP Architecture L2 Cache FPQ FPMap FPMul FPAdd FPReg Bpred IntMap IntQ IntReg IntExec LdSTQ ITB DTB ICache DCache (a) CMP with a detailed processor 33

39 Body Bias Cells We partition each core into BB cells Shapes and sizes follow functional units FGBB16 FGBB64 FGBB144 34

40 Variation Impact Frequency Vth σ/μ (a) φ=0.1 φ=0.2 φ=0.5 Leakage Power Vth σ/μ (b) 35

41 Applications of D-FGBB Operating environments Normal High Performance Low Power S-FGBB Improve chip operating point Improve chip operating point Save leakage power D-FGBB Save leakage power Increase average frequency Save leakage power 36

42 S-FGBB Improves the Chip s Operating Point BB1 NoBB S-FGBB16 S-FGBB64 S-FGBB144 frequency % % % % % % age leakage leakage leakage leakage (a) (c) (d) (e) Figure 10. kage power for a batch of 200 chips at T cal and full load under various schemes. 37 would include the NoVar chip, which is point (1,1). We then arbitrarily set the horizontal line to 0.85 of the frequency of the NoVar chip, and divide the range into four equally-spaced frequency bins. As a fraction of the NoVar frequency, the ranges of the bins are: , , , and over These bins are in the ballpark of those used in commercial processors.

43 D-FGBB Reduces Leakage Leakage Power D-FGBB Number of BB Cells (a) Total Power NoBB S-FGBB D-FGBB Large leakage reduction after binning: 28-42% More BB cells result in higher savings 38

44 Applications of D-FGBB Operating environments Normal High Performance Low Power S-FGBB Improve chip operating point Improve chip operating point Save leakage power D-FGBB Save leakage power Increase average frequency Save leakage power 39

45 D-FGBB Improves Frequency Frequency Number of BB Cells NoBB S-FGBB D-FGBB ure 15. Average frequency of the chips for different (a) Average frequency improvement 7-9% over S- FGBB and 7-16% over NoBB More BB cells result in higher increase 40

46 Power Cost Total Power Number of BB Cells Pmax NoBB S-FGBB D-FGBB re 18. Total power of the chips for different FGBB sch Significant power cost, but still within the power budget 41

47 Applications of D-FGBB Operating environments Normal High Performance Low Power S-FGBB Improve chip operating point Improve chip operating point Save leakage power D-FGBB Save leakage power Increase average frequency Save leakage power 42

48 he more aggressive BB voltage needed ces higher leakage power. The resultand D-FGBB is shown in Figure 18. cost, this mode of operation D-FGBB is only apssible performance is needed. 43 Leakage Power NoBB S-FGBB D-FGBB Number of BB Cells (a) r of BB CellsLarge leakage reduction at constant frequency: f the chips for different FGBB schemes. GBB Reduces Leakage Total Power 0.2 More BB cells result in higher savings 0 69% compared to NoBB. Even w saves substantial leakage. Figure 19(b) shows the total ent FGBB schemes, DVS, and D- by D-FGBB are still large. Spec tal power consumption by 6 19% bined with DVS, D-FGBB+DVS by 15 36% compared to S-FGBB D-FGBB Reduces Leakage Leakage Power 0.4 NoBB S-FGBB D-FGBB 10-51% vs. S-FGBB and 12-69% vs NoBB Number of BB Cells

49 Combining D-FGBB with DVFS D-FGBB targets leakage power DVFS targets mostly dynamic power Can they be combined effectively? 44

50 Combining D-FGBB with DVFS Leakage Power NoBB D-FGBB1 D-FGBB16 BB16 D-FGBB64 D-FGBB V 0.8 V 0.6 V Vdd (a) Total Power Total Power V 0.8 V 0.6 V Vdd D-FGBB scales well with DVFS S-FGBB does not scale unless calibrated at multiple voltages (b) 45

51 Conclusions D-FGBB is an effective and versatile tool to address parameter variation We show three scenarios: Normal: 28-42% leakage savings vs. S-FGBB High performance: 7-9% frequency increase Low power: 10-51% leakage reduction vs. S-FGBB Combines well with DVFS 46

52 More in our MICRO 2007 paper More details on the variation model A solution for combining D-FGBB with DVS Estimated overheads of D-FGBB More implementation details Thank you! Questions? 47