Lecture 17: Process Variations. Changes in characteristics of devices and wires. Caused by IC manufacturing process & wear-out (electromigration).

Transcription

1 EE24 - Spring 2005 Advanced Digital Integrated Circuits Lecture 7: Process Variations Variability Sources Physical Changes in characteristics of devices and wires. Caused by IC manufacturing process & wear-out (electromigration). Time scale: 0 9 sec (years). Environmental Changes in VDD, Temperature, local coupling. Caused by the specifics of the design implementation. Time scale: 0 6 to 0 9 sec (clock tick). 2

2 3 Process Variations Control of minimum features does not track feature scaling Relative device/interconnect variations increase Sources: Random dopant fluctuations Feature size, oxide thickness variations Effects: Speed Power, primary leakage Yield 4 2

3 Increasing Process Variations Original Source: Sani Nassif IBM Percentage of total variation accounted for by withindie variation(device and interconnect) Increase in variation of process parameters with scaling Worst-case design getting more expensive Better than worst-case design must be error tolerant 5 6 3

4 Vt Distribution # of Chips VTn(mv) 0.8 micron ~000 samples ~30mV High Freq High Isb High Freq Medium Isb Low Freq Low Isb 7 Sources of Variations 0000 Mean Number of Dopant Atoms Technology Node (nm) Random Dopant Fluctuations Sub-wavelength Lithography 000 Lithography 365nm Wavelength 248nm 93nm micron 80nm nm 0. 30nm Gap 00 90nm 65nm Generation 45nm 32nm 3nm EUV Source: Mark Bohr, Intel 8 4

5 9 Achieving Sub-wavelength Resolution 0 5

6 2 6

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8 5 Causes Larger Frequency Distribution Courtesy Intel 6 8

9 Frequency & SD Leakage Normalized Frequency % 20X Normalized Leakage (Isb) 0.8 micron ~000 samples Low Freq Low Isb High Freq Medium Isb High Freq High Isb Variation-tolerant Design small large Transistor size large small Logic depth power target frequency probability Balance power & frequency with variation tolerance frequency target frequency probability low high Low-Vt usage 0 less more # uarch critical paths 8 9

10 Approaches Worst-case design Leaves too many crumbs on the table. Huge concurrency overhead for performance. Regular design strategies to reduce variation Careful choice of logic styles Self-adapting design. Turns on-line knobs (Vdd, Vt) to guarantee operation of the design. Uses onetime correction for systematic errors Alternative Timing Approaches Self-timed or clockless design Defers the decisions to the system level. Comes with large overhead Pseudo-synchronous design (e.g. Razor) Allows for occasional timing errors. Limited operation range. 9 Problem: Predictability (Chip Variability) - Std library abstractions break: don t hide the details anymore, as we scale down Cu thickness distrib Cu thickness histogram Correlated random variations hit ckt level Global effects Defocus effect (grows) Exposure variation (shrinks) Defocus effect Resist effect Local printability problems Demise of context-free layout design rules 30 March 2005 Slide 20 0

11 Yesterday s Freelance Layout V dd V dd I p O p O p V ss V ss No layout restrictions 2 Transistor Orientation Restrictions V dd V dd I p O p O p V ss V ss Transistor orientation restricted to improve manufacturing control 22

12 Transistor Width Quantization V dd V dd I p O p O p V ss V ss 23 2

13 Fabrics Idea: Atomic Regularity (Make the Variablility Small Everywhere) Today s designs Starting from basic manufacturing shapes circuits logic routing everything is extremely regular Means radical re-architecting of flows How much predictability? At what cost? Initial motivation was what s after ASICs, now more generally aimed at predictability Regular/Structured Integrated System Tomorrow s designs Regular Circuits Regular Geometry Fabric 30 March 2005 Slide 28 Regular Fabrics A Plethora of Choices VPGA CMU Trade-off between area, performance, power and time-to-market to-market (factors 5 to 0) River PLA Berkeley FPGA ASPDAC, Jan Structured ASIC (e.g. LSI RapidChip)

14 Fabric Architectures: Via Patterned Gate Array Configurable with 4 masks for top vias Base architecture can be like an FPGA but replace expensive switches with mask-config vias Many possible interconnect options: std cell routing, or fully regular top-level patterned routing Network switch (80k Gates) Area (um 2 ) Slack (ns) Standard ASIC flow Regular Logic VPGA flow Array offers fully predictable geom. patterning [Pileggi, CMU] VPGA regular logic + standard cell routing 30 March 2005 Slide 30 Fabric Analysis: Enhanced Manufacturability for Regular Ckt Fabrics M4 Density of CMU VPGA FPU Cu Dishing (M4) Final Post-CMP Cu Thickness (M4) Reduced CMP effects Copper dishing < 40Å Post-CMP Copper thickness variation is less than 2-3% Highly promising as a manufacturable logic replacement structure Plated Thickness (M4) Oxide Erosion (M4) [Boning, MIT Pileggi, CMU] 30 March 2005 Slide 3 2

15 Fabric-level Custom Circuit Design: Limited-Switch Dynamic Logic (LSDL) Merges latch with every output stage Speed of domino with less power Domino LSDL [Montoye 03] LSDL: good for regularity, var tolerance Cells more regular in content and size. Less variation in pattern density. More tolerant of manufacturing variation Pattern Density Poly M Interchip+Mismatch Variation Experiment: 6-bit Kogge-Stone adders, full domino vs LDSL 58 extracted 0.8um fab run models Monte-Carlo for chip-to-chip & mismatch LDSL: good for size & speed ~ 20% less area; ~2X faster LSDL Domino [Boning, MIT] 30 March 2005 Slide 32 Fabric-Level Flow Design: Regularizing Cell-Based Flows Complementary approach: Regularize a library-based flow Every cell is identical except for vias Regularity issues handled by cell layout generators, exclusively Extends lifetime of existing flows Looking at impacts on performance Ex: granularity of available cell sizes (i.e. library size) is reduced [Sechen, Washington] 30 March 2005 Slide 33 3

16 RapidChip Platform ASIC Configurable Platform Families of pre-manufactured slices Sea of transistors for high density, high performance user-configurable logic Up to 5 layers of metal personalization Flexible approach to IP: Diffused only when performance dictates, eg high speed SerDes On-demand for most other IPs, eg processors Rich portfolio of soft IPs available 2 Dec LSI Logic Confidential LSI Logic 2004 Today s Reconfigurable FPGA Platform PowerPC Processor 400+ MHz High-speed 3.25 Gbps Serial Transceivers Programmable IO 8 Bit 36 Bit 8 Bit VCCIO Z 0Mbit Dual-Port >500 DSP datapaths Z Z Impedance Control 0 Million gates RAM Xilinx 4

17 Delay and Power Variability in CMOS Goal: Investigate the effects of variations in V th, L poly, W, t ox and V dd on the performance of a family of representative circuits. Quantify the statistical variability of circuit delay and power (active). Identify single parameter contributions to overall variability levels. Circuits under study: NAND chain (six stages) Adders (6-bits, various architectures) Logic styles: Static, Dynamic Domino, Passgate All transistor sizes optimized for minimum delay under an area constraint Experimental Setup: 90nm, pd-soi technology Industrial research site All parameter distributions set by predictive BSIMSOI models, ITRS (2003) 36 Monte Carlo Simulation I Choose circuit under study Draw all parameter values randomly from respective distributions Apply parameters to circuit to create a specific instance Submit circuit instance to SPICE simulation, measure active power and delay repeat N times Goal I: Vary all parameters simultaneously; study the statistical variability of power and delay. Variable parameters: V th, L poly, W, tox, V dd : V (mean value) Temperature held at 85 C Interdependencies between parameters reconciled within the simulation N = 200 for adders, N = 000 for NANDs The spatial correlation coefficient defines parameter matching between adjacent transistors Each parameter is assigned identically to all transistors within each circuit instance ρ is set to, indicates perfect correlation (worst-case) 37 5

18 Interdependencies Between Parameters The operating value of V th is composed of its long channel V th0 value modified by V th factors (BSIMSOI Model): V th, OPERATING V th, OPERATING V th,dibl V th,halo V th0 ( N channel, Φ M, Φ t S, ox ) V th0 + V th, BIAS ( V bs ) V th,bias V th, DIBL ( V ds, L) + V th, HALO ( N halo, L) L + V th, NarrrowWidth ( W ) Interdependencies between parameters are reconciled within each simulation by separating V th, OPERATING into independent and dependent components. 38 Choose circuit under study Monte Carlo Simulation II repeat for all p parameters Draw one parameter value randomly from its distribution, hold others at nominal Apply parameters to circuit to create a specific instance repeat N times.... Draw one parameter value randomly from its distribution, hold others at nominal Apply parameters to circuit to create a specific instance repeat N times Goal II: Isolate individual parameter contributions to overall power/delay variability Parameter distributions same as in previous setup Again, perfect spatial correlation of parameters is assumed (ρ = ) Submit circuit instance to SPICE simulation, measure active power and delay Submit circuit instance to SPICE simulation, measure active power and delay 39 6

19 NAND Chains (6-stages) Static capacitive load, C L = 0fF Static CMOS Static Passgate (LEAP) M M 2 M 3 out a M 4 b M 5 Active, FO3 load (value varies with parameter fluctuations) c M 6 Pulsed Static Dynamic Domino clk' c M M 2 x M 5 a b out clk a b M M 6 out M 2 M 3 out' M 3 c M 4 clk M 4 M 5 40 Adders Ripple carry with Manchester carry chain (passgate-based) Static 0 Carry select, logarithmic configuration bit0 Bit level C out and Sum selection Block level C out selection Cout generation 0 bit 0 bit6 0 bit3 bit2 0 bit bit7 bit3 C in bit0 bit4 bit2 bit8 bit4 bit5 bit9 C out0 bit5 C out2 C out5 C out9 C out5 Dynamic Static, Dynamic Domino, Passgate 4 7

20 Adders: CLA Trees Rippled Carries Kogge Stone, Radix 2 Sum 07 Sum 06 Sum 05 Sum 04 Sum 03 Sum 02 Sum 0 Sum 00 Sum 08 Sum 09 Sum 0 Sum Sum 2 Sum 3 Sum 4 Sum 5 Kogge Stone, Radix 4 Large stack height (static) = 8 Sum 00 Sum 0 Sum 02 Sum 03 Sum 04 Sum 05 Sum 06 Sum 07 Sum 08 Sum 09 Sum 0 Sum Sum 2 Sum 3 P,G Generation Group P,G Sum Generation Sum 5 Sum Brent-Kung Large intermediate load capacitance along critical path (Sum07 node) Han-Carlson Sum 5 Sum 4 Sum 3 Sum 2 Sum Sum 0 Sum 09 Sum 08 Sum 07 Sum 06 Sum 05 Sum 04 Sum 03 Sum 02 Sum 0 Sum 00 Sum 5 Sum 4 Sum 3 Sum 2 Sum Sum 0 Sum 09 Sum 08 Sum 07 Sum 06 Sum 05 Sum 04 Sum 03 Sum 02 Sum 0 Sum Delay, Power Variability: NAND chains Normalized Delay Variability (sigma/mean) STATIC PSCMOS LEAP DOMINO Normalized Power Variability (sigma/mean) STATIC PSCMOS LEAP DOMINO The static CMOS implementation is the most robust to process parameter variations The passgate style (LEAP) displays the highest levels of delay and power variability (30% higher than static) 43 8

21 Delay Variability: Adders MANCHESTER STATIC MANCHESTER DYNAMIC CARRY SELECT STATIC CARRY SELECT PASSGATE CARRY SELECT DYNAMIC STATIC RADIX 2 STATIC RADIX 4 PASSGATE DYNAMIC HAN-CARLSON BRENT-KUNG Normalized Delay Variability (sigma/mean) Static carry select is the most robust The three most variable are passgate-based, between 3% - 67% more spread than static carry select 44 Power Variability: Adders Normalized Power Variability (sigma/mean) MANCHESTER STATIC MANCHESTER DYNAMIC CARRY SELECT STATIC CARRY SELECT PASSGATE CARRY SELECT DYNAMIC STATIC RADIX 2 STATIC RADIX 4 PASSGATE DYNAMIC HAN-CARLSON BRENT-KUNG Most robust: static ripple with Manchester carry chain The least robust: designs with large/irregular intermediate load capacitance along critical paths (radix 4 Kogge Stone, Brent Kung) 45 9

22 Single Parameter Breakdown: NAND Chains Static capacitive load F03 load Individual Parameter Contribution to Delay Variability 45% 40% 35% 30% 25% 20% 5% 0% 5% 0% STATIC PSCMOS LEAP DOMINO Vth L Vdd tox W Individual Parameter Contribution to Delay Variability 45% 40% 35% 30% 25% 20% 5% 0% 5% 0% STATIC PSCMOS LEAP DOMINO Vth L Vdd tox W Results vary depending on final loading stage (static vs. FO3) V th is most significant contributor in all cases For active, F03 loads: Passgate design is most sensitive to V th variations Increased significance of L variations 46 Single Parameter Breakdown: Adders (Delay) 00% Normalized Individual Parameter Contribution to Delay Variability 80% 60% 40% 20% 0% MANCHESTER STATIC MANCHESTER DYNAMIC CARRY SELECT STATIC CARRY SELECT PASSGATE CARRY SELECT DYNAMIC STATIC RADIX 2 STATIC RADIX 4 PASSGATE DYNAMIC HAN-CARLSON BRENT-KUNG W tox vdd L vth V th is most significant contributor (33% average) Passgate designs are the most sensitive to V th variations L is nearly as significant (28% average) 47 0

23 Single Parameter Breakdown: Adders (Power) 00% Normalized Individual Parameter Contribution to Power Variability 80% 60% 40% 20% 0% W tox vdd L vth MANCHESTER STATIC MANCHESTER DYNAMIC CARRY SELECT STATIC CARRY SELECT PASSGATE CARRY SELECT DYNAMIC STATIC RADIX 2 STATIC RADIX 4 PASSGATE DYNAMIC HAN-CARLSON BRENT-KUNG V dd contributions dominate (4% average) V th variations are also significant (30% average) 48 Conclusions Static CMOS implementations are generally the most robust to parameter variations, for both delay and power Passgate designs display the least amount of robustness: Suffer spreads in delay and power variability between 30% 70% higher than static designs Tend to display highest sensitivity to V th variations These are worst-case results, due to the assumption of perfect parameter correlation V th variations account for 35% - 40% of delay variability Power variability trends suggest a dependence upon large or irregular intermediate load capacitances V th, L and V dd are consistently the highest contributors to both delay (85%) and power (80%) variation. 49

24 A Self-adapting Approach Motivation: Most timing variations are systematic, and can be adjusted for at start-up time using one-time calibration! Relevant parameters: T clock, V dd, V th V th control the most effective and efficient at low voltages Can be easily extended to include leakage-reduction and power-down in standby Test inputs and responses V dd T clock Test Module Module V bb Achieves the maximum power saving under technology limit Inherently improves the robustness of design timing Minimum design overhead required over the traditional design methodology 50 V th Tuning via Body Bias G S D Vbs (V) Reversed V bs Forward V bs B V th (V) Less design cost than V dd tuning Vth tunable range: >50mV for a 90nm Technology 5 2

25 Power and Timing Tradeoffs Eswitching (fj) Adaptive Tuning Worst Case, w/o Vth tuning Worst Case, w/ Vth tuning Nominal, w/o Vth tuning Nominal, w/ Vth tuning 5 0 V dd : mV 5.0E+03.0E+04.0E+05.0E+06.0E+07 Path Delay (ps) V th tuning can effectively gain performance back 52 Adaptive Body Bias-- --Experiment 5.3 mm Multiple subsites Resistor Network PD & Counter Delay CUT Resistor Network Bias Amplifier 4.5 mm Technology Number of subsites per die Body bias range Bias resolution 50nm CMOS 2 0.5V FBB to 0.5V RBB 32 mv.6 X 0.24 mm, 2 sites per die 50nm CMOS Die frequency: Min(F..F 2 ) Die power: Sum(P..P 2 ) 3

26 Adaptive Body Bias-- --Results Number of dies too slow too leaky ABB FBB RBB f target Frequency f target Accepted die 00% 60% 20% 0% nobb ABB within die ABB 97% highest bin 00% yield Higher Frequency For given Freq and Power density 00% yield with ABB 97% highest freq bin with ABB for within die variability Adaptive Approach for Dealing with Variations Source: Sam Naffziger, HP 55 4