Measurement and Optimization of Electrical Process Window

Transcription

1 Measurement and Optimization of Electrical Process Window Tuck-Boon Chan*, Abde Ali Kagalwalla, Puneet Gupta Dept. of EE, University of California Los Angeles Work partly supported by NSF and UC Discovery IMPACT. NanoCAD Lab 1

2 2 Outline Definition and evaluation of Geometric Process Window (GPW) Electrical Process Window (EPW) EPW vs GPW Improving EPW EPW Approximations

3 Process Window Definition of process window: The range of process parameters that allows circuits to operate under desired specifications [1]. Defocus Process window (gate length > 65nm) Exposure 3 Exposure = 1.0 Exposure = 0.8 Exposure = 1.0 Defocus = 160nm Defocus = 0nm Defocus = 0nm Gate Length 53nm Gate Length 87nm Gate Length 69nm [1] Mack, C. A., Legband, D. A., and Jug, S., Data analysis for photolithography, Microelectron. Eng. 46(1-4), (1999).

4 Geometric Process Window (GPW) Process parameters are within GPW iff critical dimension (CD) < allowed CD deviation Edge placement error (EPE) L nom L minlmax EPE tolerance EPE exceeds tolerance EPEs of transistors Min/max allowed EPE Layout Printed contour % EPE 2 scenarios are considered : 1. CD = L nom +/- 2*maximum EPE (W-GPW) 2. CD = L nom +/- maximum EPE (A-GPW) 4

5 5 Problems of GPW 1. Geometric tolerance does not quantify changes in electrical specifications well. Averaging across transistor segments A transistor segment may violate geometric tolerance but the transistor can work within desired electrical specification Averaging across multiple transistors Delay averages across critical path Power averages across all transistors tolerance EPE exceeds tolerance 2. Not all shapes are critical but equal effort/resources are dedicated.

6 Electrical Process Window A process point is considered within EPW iff Lower bound of allowed circuit performance Circuit performance Upper bound of allowed circuit performance Need to extract circuit performance of printed contours Modeling non-rectangular gate transistor Impact of interconnect linewidth variation is relatively smaller compared to the impact of gate length variation on transistor [2] Width variation averages over long wires. Resistance and capacitance change in opposite directions as line width changes. [2] Chan, T.-B., Ghaida, R. S., and Gupta, P.,.Electrical modeling of lithographic imperfections,. VLSI DESIGN (2010). 6

7 7 Modeling non-rectangular transistor [3] W d_i W s_i S edge W eff_i z y S middle edge L eff _i ΔV th_i V th_i L eff_i Irregular channel Sliced channel Approximate slices and extract W eff_i, L eff_i and V th_i. Evaluate and sum I eff of rectangular transistor Slice simulated transistor channel Calculate V th, effective width and length of each slice Find the total I on and I off [3] Chan, T.-B. and Gupta, P.,.On electrical modeling of imperfect diffusion patterning,. VLSI DESIGN (2010).

8 8 Delay centric EPW (DEPW) A process point is considered within DEPW iff Max( path delay) Upper bound of allowed delay deviation Assume cell delay is inversely proportional to I on Extract I on from simulated contour and original layout Path delay is the sum of delay of each cell Obtained from timing report

9 9 Leakage Power Centric EPW (PEPW) A process point is considered within PEPW iff power Upper bound of allowed leakage power deviation Leakage power is proportional to I off Extract I off from simulated contour and original layout

10 10 Combined EPW (CEPW) Process window of multiple electrical metrics : Intersection of EPWs Defocus PEPW CEPW DEPW A-GPW W-GPW Exposure

11 11 Relation between EPW and GPW GPW and EPW are defined differently Need to know relation between them for fair comparison Simulate an INV (FO4) at worst case corners of W-GPW using SPICE, measure the delay and power deviation Channel length (%) W-GPW EPE (%) A-GPW EPE (%) DEPW delay (%) PEPW power (%) Use SPICE model and layout from 45nm Nangate Open Cell library (Vdd = 1.1V, Temperature = 25 o C)

12 12 Analysis Flow Design : ISCAS-85 benchmark circuits 45nm Nangate Open Cell Library Synthesis, place and route layout Layout (original), timing report Simulate layout using different process parameters Layout after OPC Run OPC at nominal process point timing report Simulated contours Delay & Power Extraction EPW Extraction Filter printed contour with short or open circuit EPE histogram GPW Extraction

13 GPW vs EPW GPW is pessimistic because 1. GPW: Limit by worst transistor segment deviation EPW: Average deviation of each transistor segment 2. Averaging across multiple transistors Delay averages across critical path Power averages across all transistors 3. All transistors are not equally important => Delay constraint is applied on critical path only EPW is 1.5 to 6X larger than AGPW on average Defocus A-GPW Defocus DEPW Defocus PEPW Defocus CEPW Exposure Exposure Exposure Maximum feasible region Exposure 13

14 14 Improving EPWs Layout transparent process tuning Avoid major change in layout Increasing V th or gate length DEPW PEPW CEPW?? We tried : -2nm on critical +2nm on non-critical +/-2nm on all (i.e., a global CD push) +/-20mV on all (i.e., a global Vth push)

15 Normalized area Normalized area 15 Improved DEPW and PEPW Area of improved DEPWs normalized to reference DEPW c432 c c c nm on critical only -2nm on all -20mV on all +2 nm on non-critical +2nm on all +20mV on all c1908 Average Area of improved PEPWs normalized to reference PEPW c c c nm on critical only -2nm on all -20mV on all +2 nm on non-critical +2nm on all +20mV on all c1355 c1908 Average

16 Normalized area 16 Improved CEPW nm on critical only Area of improved CEPWs normalized to reference CEPW -2nm on all -20mV on all Reducing V th on all +2 nm on non-critical Improves CEPW consistently +2nm on all Can be done without knowing the locations of critical -2nm gate length bias does not work as well due to increased pinching +20mV on all c432 c499 c880 c1355 c1908 Average

17 EPW Approximation Motivation: Critical path of a design may not be provided to lithography process Method 1 : Use EPE histogram generated in OPC Estimate EPW without extracting channel shape of each transistor Approximate average delay and power deviation induced by EPEs of all transistors as an equivalent transistor Process point EPE histogram % EPE 0.2 W 0.4 W 0.3 W 0.1 W Equivalent transistor W Nominal channel length Reference transistor 17

18 18 Method 2 : Use the shape of every transistor I off of each transistor is available => No approximation on PEPW Delay deviation of each transistor : A process point is considered within DEPW iff Average delay deviation of R transistors with worst delay deviation R= 1, Lower bound of DEPW but too pessimistic R= 30, Critical path is usually more than one transistor => Average transistor stages along critical path R= Total transistors, Assume EPE distribution on critical path is similar to that of all transistor

19 c432 c499 c880 c1355 c1908 Average c432 c499 c880 c1355 c1908 Average c432 c499 c880 c1355 c1908 Average c432 c499 c880 c1355 c1908 Average c432 c499 c880 c1355 c1908 Average c432 c499 c880 c1355 c1908 Average c432 c499 c880 c1355 c1908 Average c432 c499 c880 c1355 c1908 Average Normalized area Approximation quality Reference DEPW only consider transistor along critical path but approximate DEPW uses histogram of entire design (more averaging) 80% of reference EPW EPW region and covered EPW region but not covered Out of EPW A-GPW DEPW PEPW CEPW DEPW CEPW DEPW CEPW Approximation using EPE histogram Approximation using shape Approximation using shape R=30 R= all transistors All approximations have better area coverage compared to A-GPW Low area coverage in histogram-pepw leads to poor coverage in histogram-cepw Approximation using the shape of each transistor is the best: No area out of EPW, covered 80% area of reference EPW 19

20 20 Summary We propose EPW which is a better measure of process window than conventional GPW Area of EPW is 1.5 to 6 times larger than that of GPW on average Layout transparent methods can improve EPW by 10% Approximation to EPW covers 80% of the area of reference EPW for all benchmark circuits Future work: Analyzing only representative layouts Reduce lithography simulation runtime in EPW calculation Can be used for OPC recipe optimization

21 Backup slides 21

22 Results: EPW Approximations 22