28nm and below: New Frontiers and Innovations in Design for Manufacturing. Vito Dai, Ph.D. Sr. Member of Technical Staff, DFM

Transcription

1 28nm and below: New Frontiers and Innovations in Design for Manufacturing Vito Dai, Ph.D. Sr. Member of Technical Staff, DFM

2 Outline Challenges Variability and the Limits of IC Geometrical Scaling Methodology Innovation in Design for Manufacturing Solutions Advanced Rule-Based Verification (Yield Analysis and Yield Enhancement) Si-Accurate Model-Based Printability Verification Novel Flow: 2D Shapes Pattern-Matching Based Physical Design Verification Model Accuracy and Full-Chip Performance out Compromise Manufacturing Design-Enabled Manufacturing: Faster Yield Ramp and Foundry Customer Value Vito Dai, Ph.D. Architect 2

3 Computational Technology Scaling MinPitch 2 k NA nm Technology Scaling requires increased process complexity: i.e. reduction in k 1 factor (theoretical min=0.25) 1.35 (max) Computational Technology Scaling: Systematic reduction of k 1 factor by rigorous Co-Optimization of: (1) Physical Design (Layout, Design Rules, Place and Route) (2) Process (Illumination, Lithography, Mask RET, OPC, etc.) Computational Scaling is also known as: Design-Process-Technology Co-Optimization Vito Dai, Ph.D. Architect 3

4 GLOBALFOUNDRIES has a long history in Design-Technology Co-Optimization 130nm SRAM Traditional layout 90nm SRAM Uni-directional poly DTCO 65nm SRAM Uni-directional active 45nm SRAM Immersion, uniform poly CD 32nm SRAM Double patterning 20nm SRAM Higher NA immersion Jongwook Kye - Strategic Lithography Vito Dai, Ph.D. Architect 4

5 At 28nm and below: Physical Design dependent Yield Yield Ground Rules (binary) turn into DFM Rules (continuous) 100% Traditional Design Rule 0% 0 allowed minimum space Yield Dependency for a given Design Rule, for different layout features: due to complex RET/OPC, Optical/Process effects, etc. Feature-Feature Space Vito Dai, Ph.D. Architect 5

6 At 28nm and below: Si-Accurate Model-Based Verification DRC Clean Design-Rules Compliance does NOT guarantee Yield due to: Non-Linearity Effects Induced by Sub-Wavelength Fabrication. Furthermore OPC cannot fix all Yield Limiters configurations Manufacturable Process Window Model-Based Printability Hotspots Verification DRC Clean Process Window - Yield Limiters Vito Dai, Ph.D. Architect 6

7 Rule-Based DFM (Recommended Rules) drives Physical Layout Construction Quality Productivity Vito Dai, Ph.D. Architect 7

8 Model-Based DFM (Printability Hotspots) drives Physical Layout Optimization/Compaction Layout Optimization AND Area Compaction Vito Dai, Ph.D. Architect 8

9 Novel DFM Flow: drives Full-Chip Physical Verification M01 Necking Process Hotspot Verification 2D Shape-Based Pattern Matching DRC 2 CAs printed small Vito Dai, Ph.D. Architect 9

10 : Based on 2D Shapes Pattern-Matching: 10,000X Faster than Simulation Dr. Vito Dai GLOBALFOUNDRIES IEEE Litho Workshop 2009 Vito Dai, Ph.D. Architect 10

11 Configurations + Patterns = Rules Configuration: tip-to-side : DRC constraint 60 nm DFM constraint 80 nm DRC Plus Rule Deck Dr. Vito Dai Vito Dai, Ph.D. Architect GLOBALFOUNDRIES IEEE Litho Workshop

12 # of Patterns Geometrical Clustering Dr. Vito Dai GLOBALFOUNDRIES IEEE Litho Workshop Unique 2 3 to to to 100 > 100 # of occurences of a Pattern in a Sample Layout Vito Dai, Ph.D. Architect 12

13 # of Patterns Clustering and Printability Analysis Sensitivity to Manufacturing Process Variations (mean) Vito Dai, Ph.D. Architect 13

14 provides ACCURATE and FAST DFM Physical Verification in the Design Flow Automated Layout Analysis Library of Rules Ultra-Fast Pattern-Matching in the Design Environment Industry First from GLOBALFOUNDRIES Vito Dai, Ph.D. Architect 14

15 Now: DFM Full-Chip Physical Verification at 28nm and below Rule Library Industry first Si-validated Yield-critical patterns only from available now DFM Service Encounter Virtuoso Calibre ICV/ICC Vito Dai, Ph.D. Architect 15

16 Enables DFM Physical Verification in Timing Closure Loop Traditional flow enabled flow Timing Closure Placement Placement Timing Closure Routing ECO Routing ECO STA Pattern Library Physical Verification DRC LVS Printability Simulation ECO STA Physical Verification DRC LVS Printability Simulation optional ECO Vito Dai, Ph.D. Architect 16

17 Performance of DFM Verification & Fixing: vs. Printability Simulation CPU Time in Thousands of Seconds 4 days CPU Runtime: Design Routing Simulation or 3,596 5,434 2, hours A PS A B PS B C PS C D PS D E PS E F PS F G PS G H PS H Routing CPU Time Printability Simulation CPU Time Detection Time Fixing Time DAC 2011 User Track Best Paper Pattern-based Physical Verification in the Design Flow Vito Dai, Ph.D. Architect 17

18 DFM Toolkit Roadmap and Availability DFM Focus Area Primary (Secondary) Tool 65nm-LP/G Release 65nm-LPe Release 55nm-LPe Release 45nm Release 40nm-LP/G Release 28nm Release DFM Rules and Priority Rule-Based DFM Verification, Analysis, Enhancement Design Rule Manual Mentor Calibre CFA, YA, YE Available Available Available Available Available Available Available Available Available Available Available Available Critical Area Analysis Mentor Calibre CAA Available Available Q Available Available Available (pre-release) Litho./Etch Printability Process Verification Mentor LFD Available Available Available Available Available Available (Cadence LPA) (Mx Available) (Mx Available) (TBD) (Mx Available) (TBD) X GF + EDA X X X CMP Modeling, Verification Custom Release Q Cadence CCP Available X X Available Q Mentor CMP X X X Available Q Available CND/MGC Available (pre-release) Available (pre-release) Vito Dai, Ph.D. Architect 18

19 DFM: Design For Manufacturing DEM: Design-Enabled Manufacturing DFM and DEM are 2 complementary set of methodologies, which mirror one another by tightly coupling flows in the design space process metrology and yield data in the manufacturing space. DFM provides process awareness into the design cycle through accurately calibrated models and novel verification flows (DFM sign-off). DEM enables manufacturing/design co-optimization, using automated physical design analysis and characterization which in turn drive process optimization fine-tuned to specific customer product designs. Design: DFM Process: DEM Vito Dai, Ph.D. Architect 19 19

20 DFM Enabling First-Silicon-Success DFM Solutions at GLOBALFOUNDRIES A superior portfolio of TOOLS and SERVICES DFM Yield Scoring (CAA/CFA) Hotspot Verification MAS - Rule-Based DFM Optimal Fill/CMP Modeling Vito Dai, Ph.D. Architect 20

21 DFM Si-Accurate Design Flows GLOBALFOUNDRIES is happy to announce the donation to the Si2 Process Aware Router Implementation industrial community of the complete E-DFM Design/Technology set of data structures for Co-Optimization Non-Rectangular patterns (including XML, XSD, Transistor Modeling examples and users documentations) Stress Modeling Decomposition Scoring Si-Based Timing Analysis 20nm Enablement Vito Dai, Ph.D. Architect 21