TSMC Property. The Impacts of BSIM. Sally Liu TSMC. S. Liu TSMC, Ltd Dec 13, 2012P TSMC, Ltd
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1 The Impacts of BSIM Sally Liu TSMC
2 1 The Impacts of BSIM Outline What is BSIM Industry standard Breadth and depth Moving forward
3 2 What s in a name of BSIM The making of BSIM 631 papers in IEEE Explore database by Hu s team Modeling HC, BV, PT etc in late 70 and early : 1 st paper on IGFET charge model BSIM was coined in 1987 Berkeley Short-channel IGFET Model The BSIM family BSIM, BSIM1-6 planar MOSFETs BSIM-MG, BSIM-CMG, BSIM-IMG 3D FinFETs BSIMSOI, BSIMPD, BSIM-IMG SOI MOSFETs
4 3 BSIM was born
5 4 Tip of an iceberg One team Physics Devices Laboratories Programming Academia & industries Evaluations / benchmarking Programming Laboratories Devices Physics, Enhancements / extension Applications / validation
6 5 Let the BSIM numbers speak More than 200 BSIM articles Academics (150) IEEE Explore Database Industry (40) UCB (28) 1 st Authors Honorable mentions Title (88) by UCB by academia Text (164) (17) keywords Academia (150) by industry Abstract (135)
7 6 The BSIM standard the beginning Compact model council (CMC) started before 1996 In a time of fragmented compact model development Though, de facto standard MOSFET model exists Different flavored models in alphabet SPICE s IDM s have their proprietary models & tools Cross team design hand-shakes were chaotic BSIM3v3 elected as the first CMC standard model Extensive benchmarking with cross industrial collaboration BSIM team s dedication is key to its acceptance BSIM4 (2000), BSIMSOI (2002), BSIM-CMG(2012) Critical nanometer effects Emerging new device structures
8 7 The BSIM standard now and future BSIM4 : the first CMC standard models in TMI2 TMI2: the first CMC application program interface (API),2010 HSPICE (SNSP), Spectre (CDS), Eldo (MGC) TMI2 API enables efficient macro modeling Macro modeling = intrinsic device + extrinsic effects Layout dependent effects, aging effects, restrict design rules Proven efficiency in setup time, memory usage & computing Netlist and TMI model card SPICE parser Setup built-in standard models Loading and matrix solving TMI SPICE Interface Compiled TMI model evaluation TMI.SO library
9 8 Macro modeling at nanometers Complex layout dependency mechanical stress Middle layer (MEOL) effects device local connects Restricted design rules for DFM new lithography Statistical & parametric variations local & global Self-heating effects a node of device temperature Aging effects age extrapolation & degradation Ioff Additional geometric scaling half node Idsat Poly Oxide N+ N+ Strained silicon
10 9 BSIM locomotive 16/14nm BSIM6 CMC standard??!! BSIM-CMG CMC standard TMI2 CMC standard BSIM4 CMC standard BSIM3v3 CMC standard BSIMSOI CMC standard BSIM named IGFET charge model MOS2/MOS3 IGFET model MOS1 IGFET model
11 10 BSIM portfolio 16/14nm BSIM4 BSIMPD BSIM4 published CMC published standard BSIM3v3 BSIM3 published CMC standard BSIM-CMG CMC standard TMI2 BSIM-CMG CMC BSIM6 BSIM-IMG standard published published BSIMSOI BSIM5 BSIMSOI BSIM-MG CMC published published published standard BSIM6 CMC standard??!! BSIM2 published BSIM named IGFET charge model MOS2/MOS3 IGFET model MOS1 IGFET model
12 Delta_Idsat (%) 11 BSIM4 critical features for nanometer BSIM4 OPC small feature effects Strained Silicon Stress Effect DFM-LPE Gate Tunnel Current SPA SA Well Proximity Effect M1 SPB BSIM subckt - LPE Oxide STI N+ Poly STI BSIM4 LPE Substrate STI Well PR N-well BSIM N-well Gate-induced diode leakage 15% 10% 5% 0% -5% -10% -15% STI Stress Effect BSIM subckt - LPE Effect_A Effect_B Effect_A+Effect_B SA=SB ( m)
13 12 Required basic model features G S B D Physical and accurate in inversion & accumulation regions Relevant small-geometry effects Relevant nanometer effects, e.g. halo implant, well-proximity, strained-silicon, shallow-trench stress, etc Mobility modulation effects, e.g. velocity saturation, Coulomb scattering etc Quantum-mechanical corrections Poly-depletion effects, gate-tunneling & hot-carrier leakage Non-quasi saturation (NQS) effects Charge /capacitance models conserving electric charge Noise models, including flicker and thermal
14 13 Emerging effects in deep nanometer New device structures FinFET Influence from device environment Scaling slope changing Process variation of larger percentage Random telegraph noise Self heating Aging effects
15 14 Evolution and revolution Foundry deployment 2003: Gate tunneling current in BSIM4.3 (90nm) 2004: STI stress & trap-assisted diode leakage in BSIM : WPE in BSIM4.5 (65nm) 2007: Composite STI stress by subckt macro (45/40nm) 2008: More new LDE by subckt macro (28/20nm) 2011: Aging model & FinFET model in TMI2 for beta testing Inventing FinFET IEDM 1998: A Folded channel MOSFET for Deep-sub-tenth Micron Era, Digh Hisamoto, Wen-Chin Lee, Jakub Kedzierski, Erik Anderson, Hideki Takeuchi, Kazuya Asano, Tsu-Jae King, Jeffrey Bokor, Chenming Hu (Hitachi, UCB, Lawrence Berkeley Lab, Nippon Steel, NKK) The viable transistor in sub-20nm BSIM-CMG now a CMC standard model
16 15 The deep-nano and post-silicon Compact models is pivotal in design enablement More intensive collaboration between foundry & design Early waves starts earlier Standard model and standard API key to deployment Standard models definitely for device intrinsic behaviors Macro-modeling definitely for surrounding influences Design development Models/EDA Tools Technology development Technology Parameters Designers Integrated DFM Concurrent Compact model Production Time
17 16 Semiconductor eco-system Product Definition Design Enablement Manufacturing Backend Systems Products Design IP/Library EDA Design Implementation Mask & OPC Technology Manufacturing Wafer Testing Bumping Flip Chip Final Test Industrial Interface Standards Compact model and parameters are the critical link in electrical information flow Product & Design Know-how Massive Silicon & Product Engineering Data SPEC RTL Netlist GDS Mask Wafer Sort Package Test Process Data / Models release Compile, Accumulate, & Formulate Data
18 Speed or Area 17 The best yet to come An Eco-System for Innovations Device up ASIC Device Tuning / TCAD Design Rules / Litho- OPC ET delivers performance, manufacturability, reliability in scaled dimensions Modeling pipeline Silicon Data N-1 N N+1 Data Analysis SPICE Modeling EDA Tools New / Changes is the norm New devices, new materials, new litho, new constraints, Rapid recipe changes as ET evolves / revolves Design margin / variation bounding Design Interposer packaging / Open 3DIC modeling Technology Modeling Platform LPE LVS / Interconnect modeling Library / Predictive modeling
19 18 Acknowledgements Dr. Min-Chie Jeng Dr. Bing J. Sheu Dr. K.W. Su Dr. C.K. Lin and members of TSMC Technology Modeling Division for their assistance in the preparation and their contribution in advancing compact models at foundry
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